XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 373

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Parallel Data Inputs - D1 to D6
Output Data Clock Enable - OCE
Parallel 3-state Inputs - T1 to T4
3-state Signal Clock Enable - TCE
Reset Input - SR
All incoming parallel data enters the OSERDES module through ports D1 to D6. These
ports are connected to the FPGA fabric, and can be configured from two to six bits (i.e., a
6:1 serialization). Bit widths greater than six (up to 10) can be supported by using a second
OSERDES in SLAVE mode. See
for bit ordering at the inputs and output of the OSERDES along with the corresponding bit
order of the ISERDES_NODELAY.
OCE is an active High clock enable for the data path.
All parallel 3-state signals enter the OSERDES module through ports T1 to T4. The ports
are connected to the FPGA fabric, and can be configured as one, two, or four bits.
TCE is an active High clock enable for the 3-state control path.
The reset input causes the outputs of all data flip-flops in the CLK and CLKDIV domains
to be driven Low asynchronously. OSERDES circuits running in the CLK domain where
timing is critical use an internal, dedicated circuit to retime the SR input to produce a reset
signal synchronous to the CLK domain. Similarly, there is a dedicated circuit to retime the
SR input to produce a reset signal synchronous to the CLKDIV domain. Because there are
OSERDES circuits that retime the SR input, the user is only required to provide a reset
pulse to the SR input that meets timing on the CLKDIV frequency domain (synchronous to
CLKDIV). Therefore, SR should be driven High for a minimum of one CLKDIV cycle.
When building an interface consisting of multiple OSERDES ports, all OSERDES ports
must be synchronized. The internal retiming of the SR input is designed so that all
OSERDES blocks that receive the same reset pulse come out of reset synchronized with one
another. The reset timing of multiple OSERDES ports is shown in
www.xilinx.com
OSERDES Width
Output Parallel-to-Serial Logic Resources (OSERDES)
Expansion. Refer to
Figure 8-20, page
Figure 8-3, page 356
381.
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