XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 380

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 8: Advanced SelectIO Logic Resources
380
Timing Characteristics of 4:1 DDR 3-State Controller Serialization
The second word IJKLMNOP is sampled into the master and slave OSERDES from the D1–
D6 and D3–D4 inputs, respectively.
Clock Event 4
Between Clock Events 3 and 4, the entire word ABCDEFGH is transmitted serially on OQ,
a total of eight bits transmitted in one CLKDIV cycle.
The data bit I appears at OQ four CLK cycles after IJKLMNOP is sampled into the
OSERDES. This latency is consistent with the
OSERDES latency of four CLK cycles.
The operation of a 3-State Controller is illustrated in
case shown in a bidirectional system where the IOB must be frequently 3-stated.
X-Ref Target - Figure 8-19
OBUFT.O
CLKDIV
Figure 8-19: OSERDES Data Flow and Latency in 4:1 DDR Mode
CLK
OQ
TQ
D1
D2
D3
D4
T1
T2
T3
T4
www.xilinx.com
1
1
1
1
A
B
C
D
Event 1
Clock
A B C D E F G H
G
E
H
F
0
0
1
0
Table 8-10
Clock
Event 2
E F
Figure
K
J
L
I
listing of a 8:1 DDR mode
H
8-19. The example is a 4:1 DDR
I J K L
1
1
1
1
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_8_19_100307