XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 43

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
BUFR Primitive
the global clock tree. Each BUFR can drive the four regional clock nets in the region it is
located, and the four clock nets in the adjacent clock regions (up to three clock regions).
Unlike BUFIOs, BUFRs can drive the I/O logic and logic resources (CLB, block RAM, etc.)
in the existing and adjacent clock regions. BUFRs can be driven by clock capable pins or
local interconnect. In addition, BUFR is capable of generating divided clock outputs with
respect to the clock input. The divide values are an integer between one and eight. BUFRs
are ideal for source-synchronous applications requiring clock domain crossing or serial-to-
parallel conversion. There are two BUFRs in a typical clock region (four regional clock
networks). The center column does not have BUFRs.
BUFR is a clock-in/clock-out buffer with the capability to divide the input clock frequency.
X-Ref Target - Figure 1-20
Table 1-7: BUFR Port List and Definitions
Additional Notes on the CE Pin
When CE is asserted/deasserted, the output clock signal turns on/off. When global
set/reset (GSR) signal is High, BUFR does not toggle, even if CE is held High. The BUFR
output toggles after the GSR signal is deasserted when a clock is on the BUFR input port.
O
CE
CLR
I
Port Name
Output
Input
Input
Input
Type
www.xilinx.com
CLR
Figure 1-20: BUFR Primitive
CE
I
1
1
1
1
Width
ug190_1_20_032306
Clock output port
Clock enable port. Cannot be used in
BYPASS mode.
Asynchronous clear for the divide
logic, and sets the output Low. Cannot
be used in BYPASS mode.
Clock input port
O
Regional Clocking Resources
Definition
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