XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 54

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 2: Clock Management Technology
54
DCM Clock Output Ports
Phase-Shift Enable Input - PSEN
Dynamic Reconfiguration Data Input - DI[15:0]
Dynamic Reconfiguration Address Input - DADDR[6:0]
Dynamic Reconfiguration Write Enable Input - DWE
Dynamic Reconfiguration Enable Input - DEN
1x Output Clock - CLK0
The phase-shift enable (PSEN) input signal must be synchronous with PSCLK. A variable
phase-shift operation is initiated by the PSEN input signal. It must be activated for one
period of PSCLK. After PSEN is initiated, the phase change is gradual with completion
indicated by a High pulse on PSDONE. There are no sporadic changes or glitches on any
output during the phase transition. From the time PSEN is enabled until PSDONE is
flagged, the DCM output clock moves bit-by-bit from its original phase shift to the target
phase shift. The phase shift is complete when PSDONE is flagged. PSEN must be tied to
ground when the CLKOUT_PHASE_SHIFT attribute is set to NONE or FIXED.
shows the timing for this input.
The dynamic reconfiguration data (DI) input bus provides reconfiguration data for
dynamic reconfiguration. When not used, all bits must be assigned zeros. See the Dynamic
Reconfiguration chapter of the Virtex-5 FPGA Configuration Guide for more information.
The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration
address for the dynamic reconfiguration. When not used, all bits must be assigned zeros
and the DO output bus reflects the DCM’s status. See the Dynamic Reconfiguration
chapter of the Virtex-5 FPGA Configuration Guide for more information.
The dynamic reconfiguration write enable (DWE) input pin provides the write enable
control signal to write the DI data into the DADDR address. When not used, it must be tied
Low. See the Dynamic Reconfiguration chapter of the Virtex-5 FPGA Configuration Guide for
more information.
The dynamic reconfiguration enable (DEN) input pin provides the enable control signal to
access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is
not used, DEN must be tied Low. When DEN is tied Low, DO reflects the DCM status
signals. See the Dynamic Reconfiguration chapter of the Virtex-5 FPGA Configuration Guide
for more information.
A DCM provides nine clock outputs with specific frequency and phase relationships.
When CLKFB is connected, all DCM clock outputs have a fixed phase relationship to
CLKIN. When CLKFB is not connected, the DCM outputs are not phase aligned. However,
the phase relationship between all output clocks is preserved.
The CLK0 output clock provides a clock with the same frequency as the DCM’s effective
CLKIN frequency. By default, the effective input clock frequency is equal to the CLKIN
frequency. Set the CLKIN_DIVIDE_BY_2 attribute to TRUE to make the effective CLKIN
frequency ½ the actual CLKIN frequency. The
provides further information. When CLKFB is connected, CLK0 is phase aligned to
CLKIN.
www.xilinx.com
CLKIN_DIVIDE_BY_2 Attribute
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
description
Figure 2-6