XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 72

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 2: Clock Management Technology
72
Phase-Shift Overflow
Phase-Shift Characteristics
The phase-shift overflow (DO[0]) status signal is asserted when either of the following
conditions is true:
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The DCM is phase-shifted beyond the allowed phase-shift value. In this case, the
phase-shift overflow signal is asserted High when the phase shift is decremented
beyond –255 and incremented beyond +255 for VARIABLE_CENTER mode,
incremented beyond +255 for VARIABLE_POSITIVE mode, or decremented beyond 0
and incremented beyond 1023 for DIRECT mode.
The DCM is phase-shifted beyond the absolute range of the phase-shift delay line. In
this case, the phase-shift overflow signal is asserted High when the phase-shift in time
(ns) exceeds the ±FINE_SHIFT_RANGE/2 in the VARIABLE_CENTER mode, the
+FINE_SHIFT_RANGE in the VARIABLE_POSITIVE mode, or exceeds 0 to
+FINE_SHIFT_RANGE in the DIRECT mode. The phase-shift overflow signal can
toggle once it is asserted. The condition determining if the delay line is exceeded is
calibrated dynamically. Therefore, at the boundary of exceeding the delay line, it is
possible for the phase-shift overflow signal to assert and deassert without a change in
phase shift. Once asserted, it remains asserted for at least 40 CLKIN cycles. If the
DCM is operating near the FINE_SHIFT_RANGE limit, do not use the phase-shift
overflow signal as a flag to reverse the phase shift direction. When the phase-shift
overflow is asserted, deasserted, then asserted again in a short phase shift range, it
can falsely reverse the phase shift direction. Instead, use a simple counter to track the
phase shift value and reverse the phase shift direction (PSINCDEC) only when the
counter reaches a previously determined maximum/minimum phase shift value. For
example, if the phase shift must be within 0 to 128, set the counter to toggle
PSINCDEC when it reaches 0 or 128.
Offers fine-phase adjustment with a resolution of ±1/256 of the clock period (or ± one
DCM_TAP, whichever is greater). It can be dynamically changed under user control.
The phase-shift settings affect all nine DCM outputs.
V
In either fixed or variable mode, the phase-shift range can be extended by choosing
CLK90, CLK180, or CLK270, rather than CLK0, choosing CLK2X180 rather than
CLK2X, or choosing CLKFX180 rather than CLKFX. Even at 25 MHz (40 ns period),
the fixed mode coupled with the various CLK phases allows shifting throughout the
entire input clock period range.
MAX_RANGE mode extends the phase-shift range.
The phase-shifting (DPS) function in the DCM requires the CLKFB for delay
adjustment.
Because CLKFB must be from CLK0, the DLL output is used. The minimum CLKIN
frequency for the DPS function is determined by DLL frequency mode.
CC
and temperature do not affect the phase shift except in direct phase-shift mode.
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010