XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 84

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 2: Clock Management Technology
DCM Timing Models
X-Ref Target - Figure 2-17
84
CLKFX180
LOCKED
CLK180
CLKDV
CLKFX
CLK90
CLKIN
CLK0
RST
Reset/Lock
The following timing diagrams describe the behavior of the DCM clock outputs under four
different conditions:
1.
2.
3.
4.
In
clocks are stabilized to the desired values, and the LOCKED signal is asserted.
•
•
•
Figure
Reset/Lock
Fixed-Phase Shifting
Variable-Phase Shifting
Status Flags
Prior to Clock Event 1
Prior to clock event 1, the DCM is locked. All clock outputs are in phase with the
correct frequency and behavior.
Clock Event 1
Some time after clock event 1 the reset signal is asserted at the (RST) pin. While reset is
asserted, all clock outputs become a logic zero. The reset signal is an asynchronous
reset. Note: the diagram is not shown to scale. For the DCM to operate properly, the
reset signal must be asserted for at least three CLKIN periods.
Clock Event 2
Clock event 2 occurs a few cycles after reset is asserted and deasserted. At clock event
2, the lock process begins. At time LOCK_DLL, after clock event 2, if no fixed phase
shift was selected then all clock outputs are stable and in phase. LOCKED is also
asserted to signal completion.
2-17, the DCM is already locked. After the reset signal is applied, all output
Figure 2-17: RESET/LOCK Example
1
3 Periods
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2
LOCK
DLL
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_2_18_042406