XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 92

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 3: Phase-Locked Loops (PLLs)
General Usage Description
92
PLL Primitives
PLL_BASE Primitive
Figure 3-4
X-Ref Target - Figure 3-4
The PLL_BASE primitive provides access to the most frequently used features of a stand
alone PLL. Clock deskew, frequency synthesis, coarse phase shifting, and duty cycle
programming are available to use with the PLL_BASE. The ports are listed in
Table 3-1: PLL_BASE Ports
Clock Input
Control Inputs
Clock Output
Status and Data Outputs
Description
CLKIN1
CLKFBIN
RST
shows the two Virtex-5 FPGA PLL primitives, PLL_BASE and PLL_ADV.
PLL_BASE
CLKFBOUT
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
LOCKED
www.xilinx.com
CLKIN, CLKFBIN
RST
CLKOUT0 to CLKOUT5, CLKFBOUT
LOCKED
Figure 3-4: PLL Primitives
Port
CLKIN1
CLKIN2
CLKFBIN
RST
CLKINSEL
DADDR[4:0]
DI[15:0]
DWE
DEN
DCLK
REL
PLL_ADV
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
CLKOUTDCM0
CLKOUTDCM1
CLKOUTDCM2
CLKOUTDCM3
CLKOUTDCM4
CLKOUTDCM5
CLKFBDCM
CLKFBOUT
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
LOCKED
DO[15:0]
UG190_c3_04_022709
DRDY
Table
3-1.