XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 96

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 3: Phase-Locked Loops (PLLs)
Table 3-3: PLL Ports
96
DADDR[4:0]
CLKINSEL
Pin Name
CLKFBIN
CLKIN1
CLKIN2
RST
PLL Ports
Determine the M and D Values
possible output frequencies for the second output frequency. Continue this process until all
the output frequencies are selected.
The constraints used to determine the allowed M and D values are shown in the following
equations:
Determining the input frequency can result in several possible M and D values. The next
step is to determine the optimum M and D values. The starting M value is first determined.
This is based off the VCO target frequency, the ideal operating frequency of the VCO.
The goal is to find the M value closest to the ideal operating point of the VCO. The
minimum D value is used to start the process. The goal is to make D and M values as small
as possible while keeping ƒ
Table 3-3
Input
Input
Input
Input
Input
Input
I/O
summarizes the PLL ports.
General clock input.
Secondary clock input to dynamically switch the PLL reference clock.
Feedback clock input.
Signal controls the state of the input mux, High = CLKIN1, Low = CLKIN2
Asynchronous reset signal. The RST signal is an asynchronous reset for the PLL. The
PLL will synchronously re-enable itself when this signal is released (i.e., PLL re-
enabled). A reset is required when the input clock conditions change (e.g.,
frequency).
The dynamic reconfiguration address (DADDR) input bus provides a
reconfiguration address for the dynamic reconfiguration. When not used, all bits
must be assigned zeros.
M
M
MAX
MIN
D
M
D
MAX
IDEAL
=
MIN
www.xilinx.com
=
rounddown
VCO
⎛
⎝
roundup
=
=
=
rounddown
as high as possible.
roundup
D
----------------------------------------------- -
MIN
Table 3-4
f
----------------------- -
VCOMIN
D
------------------------------------------------- -
×
f
MAX
Pin Description
------------------------ -
f
IN
f
PFD MAX
IN
f
VCOMAX
----------------------- -
f
PFD MIN
f
IN
×
lists the PLL attributes.
f
⎞
⎠
f
IN
IN
f
×
VCOMAX
D
MIN
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Equation 3-3
Equation 3-4
Equation 3-5
Equation 3-6
Equation 3-7