FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Table 27: GTP_DUAL Tile Quiescent Supply Current
Symbol
I
Quiescent MGTAVTTTX (transmitter termination) supply current
AVTTTXQ
I
Quiescent MGTAVCCPLL (PLL) supply current
AVCCPLLQ
I
Quiescent MGTAVTTRX (receiver termination) supply current. Includes
AVTTRXQ
MGTAVTTRXCQ.
I
Quiescent MGTAVCC (analog) supply current
AVCCQ
Notes:
1.
Typical values are specified at nominal voltage, 25°C.
2.
Device powered and unconfigured.
3.
Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER
Analyzer (XPA) tools.
4.
GTP_DUAL tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of
available GTP_DUAL tiles in the target LXT or SXT device.
GTP_DUAL Tile DC Input and Output Levels
Table 28
summarizes the DC output specifications of the GTP_DUAL tiles in Virtex-5 FPGAs.
ended output voltage swing.
Figure 2
Consult UG196:Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further details.
Table 28: GTP_DUAL Tile DC Specifications
Symbol
DC Parameter
Differential peak-to-peak input
DV
voltage
PPIN
Absolute input voltage
V
IN
Common mode input voltage
V
CMIN
Differential peak-to-peak output
DV
PPOUT
(1)
voltage
Single-ended output voltage
V
SEOUT
(1)
swing
Common mode output voltage
V
CMOUT
R
Differential input resistance
IN
R
Differential output resistance
OUT
T
Transmitter output skew
OSKEW
C
Recommended external AC coupling capacitor
EXT
Notes:
1.
The output swing and preemphasis levels are programmable using the attributes discussed in UG196:Virtex-5 FPGA RocketIO GTP
Transceiver User Guide and can result in values lower than reported in this table.
2.
Values outside of this range can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 1
+V
P
N
0
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
shows the peak-to-peak differential output voltage.
Conditions
External AC coupled ≤ 3.2 Gb/s
External AC coupled > 3.2 Gb/s
DC coupled
DC coupled
MGTAVTTRX = 1.2V
TXBUFDIFFCTRL = 000,
TX_DIFF_BOOST = ON
TXBUFDIFFCTRL = 000,
TX_DIFF_BOOST = ON
Equation based
MGTAVTTTX = 1.2V
(2)
Figure 1: Single-Ended Output Voltage Swing
www.xilinx.com
(1)
Typ
Max
Units
8.5
18
8
18
0.1
0.8
2.5
11
Figure 1
shows the single-
Min
Typ
Max
150
2000
180
2000
–400
MGTAVTTRX
+ 400
up to 1320
800
1400
700
1200 – Amplitude/2
90
100
120
90
100
120
15
75
100
200
V
SEOUT
ds202_01_051607
mA
mA
mA
mA
Units
mV
mV
mV
mV
mV
mV
mV
Ω
Ω
ps
nF
14