XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 15

FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part Number
XC5VLX50T-1FFG665C
Description
FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
2211840
No. Of I/o's
360
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1565

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X-Ref Target - Figure 2
Table 29
voltage swing.
RocketIO GTP Transceiver User Guide for further details.
Table 29: GTP_DUAL Tile Clock DC Input Specifications
X-Ref Target - Figure 3
X-Ref Target - Figure 4
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
Symbol
V
V
+V
–V
MIN
+V
+V
C
–V
V
R
IDIFF
0
EXT
0
0
ISE
IN
= 0V and V
summarizes the DC specifications of the clock input of the GTP_DUAL tile.
Figure 4
P
N
P–N
Differential peak-to-peak input voltage
Single-ended input voltage
Differential input resistance
Required external AC coupling capacitor
MAX
= 1200mV
shows the peak-to-peak differential clock input voltage swing. Consult UG196: Virtex-5 FPGA
Figure 3: Single-Ended Clock Input Voltage Swing Peak-to-Peak
Figure 4: Differential Clock Input Voltage Swing Peak-to-Peak
P – N
DC Parameter
Figure 2: Peak-to-Peak Differential Output Voltage
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(1)
Conditions
Figure 3
Min
200
100
80
75
shows the single-ended input
Typ
800
400
105
100
2000
1000
Max
130
200
ds202_02_081809
ds202_03_052708
ds202_04_052708
DV
V
V
PPOUT
IDIFF
ISE
Units
mV
mV
nF
Ω
15

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