FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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GTP_DUAL Tile Switching Characteristics
Consult UG196:Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further information.
Table 30: GTP_DUAL Tile Performance
Symbol
F
Maximum GTP transceiver data rate
GTPMAX
F
Maximum PLL frequency
GPLLMAX
F
Minimum PLL frequency
GPLLMIN
Table 31: Dynamic Reconfiguration Port (DRP) in the GTP_DUAL Tile Switching Characteristics
Symbol
F
GTP DCLK (DRP clock) maximum frequency
GTPDRPCLK
Table 32: GTP_DUAL Tile Reference Clock Switching Characteristics
Symbol
Description
F
Reference clock frequency range
GCLK
T
Reference clock rise time
RCLK
T
Reference clock fall time
FCLK
T
Reference clock duty cycle
DCREF
T
Reference clock total jitter, peak-peak
GJTT
T
Clock recovery frequency acquisition
LOCK
time
T
Clock recovery phase acquisition time
PHASE
Notes:
1.
The clock from the GTP_DUAL differential clock pin pair can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to
1 Gb/s.
2.
For reference clock rates above 325 MHz, a duty cycle of 45% to 55% must be maintained.
3.
Measured at the package pin. GTP_DUAL jitter characteristics measured using a clock with specification T
X-Ref Target - Figure 5
80%
20%
T
FCLK
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
Description
Conditions
(1)
CLK
20% – 80%
80% – 20%
(2)
CLK
(3)
CLK
Initial PLL lock
Lock to data after PLL has
locked to the reference clock
T
RCLK
Figure 5: Reference Clock Timing Parameters
www.xilinx.com
Speed Grade
Units
-3
-2
-1
3.75
3.75
3.2
Gb/s
2.0
2.0
2.0
GHz
1.0
1.0
1.0
GHz
Speed Grade
Units
-3
-2
-1
200
175
150
MHz
All Speed Grades
Units
Min
Typ
Max
60
350
MHz
200
400
ps
200
400
ps
40
50
60
%
40
ps
1
ms
200
µs
.
GJTT
ds202_05_100506
16