FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Table 35: GTP_DUAL Tile Receiver Switching Characteristics
Symbol
F
Serial data rate
GTPRX
OOB detect threshold
R
XOOBVDPP
peak-to-peak
Receiver spread-spectrum
R
XSST
(1)
tracking
R
Run length (CID)
XRL
Data/REFCLK PPM offset
R
XPPMTOL
(2)
tolerance
(4)
SJ Jitter Tolerance
JT_SJ
Sinusoidal Jitter
3.75
JT_SJ
Sinusoidal Jitter
3.2
JT_SJ
Sinusoidal Jitter
2.50
JT_SJ
Sinusoidal Jitter
2.00
JT_SJ
Sinusoidal Jitter
1.00
JT_SJ
Sinusoidal Jitter
500
JT_SJ
Sinusoidal Jitter
500
JT_SJ
Sinusoidal Jitter
100
SJ Jitter Tolerance with Stressed Eye
Total Jitter with Stressed
JT_TJSE
3.2
(6)
Eye
Sinusoidal Jitter with
JT_SJSE
3.2
Stressed Eye
Notes:
1.
Using PLL_RXDIVSEL_OUT = 1 only.
2.
Indicates the maximum offset between the receiver reference clock and the serial data. For example, a reference clock with ±100 ppm
resolution results in a maximum offset of 200 ppm between the reference clock and the serial data.
3.
CDR 1st-order step size set to 2.
4.
All jitter values are based on a Bit Error Ratio of 1e
5.
Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
6.
Stimulus signal includes 0.4UI of DJ and 0.17UI of RJ. RX equalizer is enabled.
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
RX oversampler not enabled
RX oversampler enabled
OOBDETECT_THRESHOLD = 100
Modulated @ 33 KHz
Internal AC capacitor bypassed
nd
CDR 2
-order loop disabled with
PLL_RXDIVSEL_OUT = 1
nd
CDR 2
-order loop disabled with
PLL_RXDIVSEL_OUT = 2
nd
CDR 2
-order loop disabled with
PLL_RXDIVSEL_OUT = 4
nd
CDR 2
-order loop enabled
(5)
3.75 Gb/s
(5)
3.20 Gb/s
(5)
2.50 Gb/s
(5)
2.00 Gb/s
(5)
1.00 Gb/s
(5)
500 Mb/s
(5)
500 Mb/s OS
(5)
100 Mb/s OS
(4)
3.20 Gb/s
3.20 Gb/s
(6)
–12
.
www.xilinx.com
Min
Typ
Max
0.5
F
GTPMAX
0.1
0.5
60
105
165
–5000
0
150
–200
200
(3)
–200
200
(3)
–100
100
(3)
–1000
1000
0.30
0.40
0.40
0.40
0.30
0.30
0.30
0.30
0.87
0.30
Units
Gb/s
Gb/s
mV
ppm
UI
ppm
ppm
ppm
ppm
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
18