FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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GTX_DUAL Tile Switching Characteristics
Consult UG198:Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further information.
Table 42: GTX_DUAL Tile Performance
Symbol
F
Maximum GTX transceiver data rate
GTXMAX
F
Maximum PLL frequency
GPLLMAX
F
Minimum PLL frequency
GPLLMIN
Table 43: Dynamic Reconfiguration Port (DRP) in the GTX_DUAL Tile Switching Characteristics
Symbol
F
GTX DCLK (DRP clock) maximum frequency
GTXDRPCLK
Table 44: GTX_DUAL Tile Reference Clock Switching Characteristics
Symbol
Description
F
Reference clock frequency range
GCLK
T
Reference clock rise time
RCLK
T
Reference clock fall time
FCLK
T
Reference clock duty cycle
DCREF
T
Reference clock total jitter
GJTT
T
Clock recovery frequency acquisition
LOCK
time
T
Clock recovery phase acquisition time
PHASE
Notes:
1.
GREFCLK can be used for serial bit rates up to 1 Gb/s; however, Jitter Specifications are not guaranteed when using GREFCLK.
2.
GTX_DUAL jitter characteristics measured using a clock with specification T
with link margin trade off.
3.
The selection of the reference clock is application dependent. This parameter describes the quality of the reference clock used during
transceiver jitter characterization - see
X-Ref Target - Figure 10
80%
20%
T
FCLK
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
Description
Conditions
(1)
CLK
20% – 80%
80% – 20%
CLK
(2, 3)
At 100 KHz
At 1 MHz
Initial PLL lock
Lock to data after PLL has
locked to the reference clock
GJTT
Table 46
and
Table
47.
T
RCLK
Figure 10: Reference Clock Timing Parameters
www.xilinx.com
Speed Grade
-3
-2
6.5
6.5
4.25
3.25
3.25
3.25
1.48
1.48
1.48
Speed Grade
-3
-2
200
175
150
All Speed Grades
Min
Typ
Max
60
650
200
200
40
50
60
–145
–150
0.25
1
200
. A reference clock with higher phase noise can be used
ds202_05_100506
Units
-1
Gb/s
GHz
GHz
Units
-1
MHz
Units
MHz
ps
ps
%
dBc/Hz
dBc/Hz
ms
µs
22