FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Table 47: GTX_DUAL Tile Receiver Switching Characteristics (Cont’d)
Symbol
JT_SJ
Sinusoidal Jitter
750
JT_SJ
Sinusoidal Jitter
150
SJ Jitter Tolerance with Stressed Eye
Total Jitter with Stressed
JT_TJSE
4.25
(7)
Eye
Sinusoidal Jitter with
JT_SJSE
4.25
Stressed Eye
Notes:
1.
Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2.
Indicates the maximum offset between the receiver reference clock and the serial data. For example, a reference clock with ±100 ppm
resolution results in a maximum offset of 200 ppm between the reference clock and the serial data.
3.
All jitter values are based on a Bit Error Ratio of 1e
4.
Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
5.
PLL frequency at 1.6 GHz and OUTDIV = 1.
6.
GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed.
7.
Composite jitter with RX equalizer enabled. DFE disabled.
CRC Block Switching Characteristics
Table 48: CRC Block Switching Characteristics
Symbol
F
CRCCLK maximum frequency
CRC
Ethernet MAC Switching Characteristics
Consult UG194: Virtex-5 FPGA Tri-mode Ethernet Media Access Controller User Guide for further information.
Table 49: Maximum Ethernet MAC Performance
Symbol
Description
F
Client interface maximum frequency
TEMACCLIENT
F
Physical interface maximum frequency
TEMACPHY
Endpoint Block for PCI Express Designs Switching Characteristics
Consult UG197: Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs User Guide for further information.
Table 50: Maximum Performance for PCI Express Designs
Symbol
F
Core clock maximum frequency
PCIECORE
F
User clock maximum frequency
PCIEUSER
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
(4)(6)
750 Mb/s
(4)(6)
150 Mb/s
(3)
4.25 Gb/s
4.25 Gb/s
(7)
–12
.
Description
Conditions
10 Mb/s – 8-bit width
100 Mb/s – 8-bit width
1000 Mb/s – 8-bit width
2000 Mb/s – 16-bit width
10 Mb/s – 4-bit width
100 Mb/s – 4-bit width
1000 Mb/s – 8-bit width
2000 Mb/s – 8-bit width
Description
www.xilinx.com
Min
Typ
Max
Units
0.57
UI
0.57
UI
0.69
UI
0.1
UI
Speed Grade
Units
-3
-2
-1
325
325
270
MHz
Speed Grade
Units
-3
-2
-1
1.25
1.25
1.25
MHz
12.5
12.5
12.5
MHz
125
125
125
MHz
125
125
125
MHz
2.5
2.5
2.5
MHz
25
25
25
MHz
125
125
125
MHz
250
250
250
MHz
Speed Grade
Units
-3
-2
-1
250
250
250
MHz
250
250
250
MHz
25