FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Table 52: Register-to-Register Performance (Cont’d)
Description
Dedicated Arithmetic Logic
DSP48E Quad 12-bit Adder/Subtracter
DSP48E Dual 24-bit Adder/Subtracter
DSP48E 48-bit Adder/Subtracter
DSP48E 48-bit Counter
DSP48E 48-bit Comparator
DSP48E 25 x 18 bit Pipelined Multiplier
DSP48E Direct 4-tap FIR Filter Pipelined
DSP48E Systolic n-tap FIR Filter Pipelined
Notes:
1.
Device used is the XC5VLX50T- FF1136
Table 53: Interface Performances
Description
Networking Applications
(1)
SFI-4.1 (SDR LVDS Interface)
(2)
SPI-4.2 (DDR LVDS Interface)
Memory Interfaces
(3)
DDR
(4)
DDR2
(5)
QDR II SRAM
(6)
RLDRAM II
Notes:
1.
Performance defined using design implementation described in application note XAPP856: SFI-4.1 16-Channel SDR Interface with Bus
Alignment
2.
Performance defined using design implementation described in application note XAPP860: 16-Channel, DDR LVDS Interface with Real-time
Window Monitoring
3.
Performance defined using design implementation described in application note XAPP851: DDR SDRAM Controller
4.
Performance defined using design implementation described in application note XAPP858: High-Performance DDR2 SDRAM Interface Data
Capture
5.
Performance defined using design implementation described in application note XAPP853: QDRII SRAM Interface
6.
Performance defined using design implementation described in application note XAPP852: Synthesizable RLDRAM II Controller
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Register-to-Register (with I/O Delays)
Speed Grade
-3
-2
550
500
550
500
550
500
550
500
550
500
550
500
510
458
550
500
Speed Grade
-3
-2
710 MHz
710 MHz
1.25 Gb/s
1.25 Gb/s
200 MHz
200 MHz
333 MHz
300 MHz
300 MHz
300 MHz
333 MHz
300 MHz
www.xilinx.com
Units
-1
450
MHz
450
MHz
450
MHz
450
MHz
450
MHz
450
MHz
397
MHz
450
MHz
-1
645 MHz
1.0 Gb/s
200 MHz
267 MHz
250 MHz
250 MHz
29