FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4” of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4” trace is
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in
Figure 11
X-Ref Target - Figure 11
V
REF
R
FPGA Output
REF
V
(voltage level when taking
delay measurement)
C
REF
(probe capacitance)
Figure 11: Single Ended Test Setup
Table 59: Output Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
LVCMOS, 1.2V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
X-Ref Target - Figure 12
FPGA Output
and
Figure
12.
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
Parameters V
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
MEAS
method:
1. Simulate the output driver of choice into the generalized
test setup, using values from
2. Record the time to V
DS202_06_111608
3. Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
4. Record the time to V
5. Compare the results of steps 2 and 4. The increase or
decrease in delay yields the actual propagation delay of
the PCB trace.
I/O Standard
Attribute
LVTTL (all)
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3 (rising edge)
PCI33_3 (falling edge)
PCI66_3 (rising edge)
PCI66_3 (falling edge)
PCIX (rising edge)
PCIX (falling edge
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
www.xilinx.com
C
R
REF
REF
ds202_12_042808
Figure 12: Differential Test Setup
, R
, C
, and V
fully describe
REF
REF
REF
MEAS
Table
59.
.
MEAS
.
MEAS
(1)
R
C
V
REF
REF
MEAS
(Ω)
(pF)
(V)
1M
0
1.4
1M
0
1.65
1M
0
1.25
1M
0
0.9
1M
0
0.75
1M
0
0.6
(2)
25
10
0.94
(2)
25
10
2.03
(2)
25
10
0.94
(2)
25
10
2.03
(3)
25
10
0.94
(3)
25
10
2.03
25
0
0.8
25
0
1.0
50
0
V
REF
25
0
V
REF
50
0
0.9
+
V
MEAS
V
REF
(V)
0
0
0
0
0
0
0
3.3
0
3.3
3.3
1.2
1.5
0.75
0.75
1.5
38