FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Table 61: OLOGIC Switching Characteristics
Symbol
Setup/Hold
T
/T
D1/D2 pins Setup/Hold with respect to CLK
ODCK
OCKD
T
/T
OCE pin Setup/Hold with respect to CLK
OOCECK
OCKOCE
T
/T
SR/REV pin Setup/Hold with respect to CLK
OSRCK
OCKSR
T
/T
T1/T2 pins Setup/Hold with respect to CLK
OTCK
OCKT
T
/T
TCE pin Setup/Hold with respect to CLK
OTCECK
OCKTCE
Combinatorial
T
D1 to OQ out or T1 to TQ out
DOQ
Sequential Delays
T
CLK to OQ/TQ out
OCKQ
T
SR/REV pin to OQ/TQ out
RQ
T
Global Set/Reset to Q outputs
GSRQ
Set/Reset
T
Minimum Pulse Width, SR/REV inputs
RPW
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
www.xilinx.com
Speed Grade
Units
-3
-2
-1
0.30
0.36
0.44
ns
–0.21
–0.21
–0.21
0.16
0.19
0.23
ns
–0.07
–0.07
–0.07
0.93
1.02
1.16
ns
–0.20
–0.20
–0.20
0.28
0.34
0.41
ns
–0.18
–0.18
–0.18
0.20
0.23
0.29
ns
–0.06
–0.06
–0.06
0.62
0.70
0.83
ns
0.61
0.62
0.62
ns
1.63
1.89
2.27
ns
7.30
7.30
10.10
ns
0.80
0.98
1.25
ns, Min
41