FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Table 65: CLB Switching Characteristics (Cont’d)
Symbol
T
CX inputs to CMUX output
CXB
T
CX inputs to DMUX output
CXD
T
DX inputs to DMUX output
DXD
T
An input to COUT output
OPCYA
T
Bn input to COUT output
OPCYB
T
Cn input to COUT output
OPCYC
T
Dn input to COUT output
OPCYD
T
AX input to COUT output
AXCY
T
BX input to COUT output
BXCY
T
CX input to COUT output
CXCY
T
DX input to COUT output
DXCY
T
CIN input to COUT output
BYP
T
CIN input to AMUX output
CINA
T
CIN input to BMUX output
CINB
T
CIN input to CMUX output
CINC
T
CIN input to DMUX output
CIND
Sequential Delays
T
Clock to AQ – DQ outputs
CKO
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
T
/T
AX – DX input to CLK on A – D Flip Flops
DICK
CKDI
T
DX input to CLK when used as REV
RCK
T
/T
CE input to CLK on A – D Flip Flops
CECK
CKCE
T
/T
SR input to CLK on A – D Flip Flops
SRCK
CKSR
T
/T
CIN input to CLK on A – D Flip Flops
CINCK
CKCIN
Set/Reset
T
SR input minimum pulse width
SRMIN
T
Delay from SR or REV input to AQ – DQ flip-flops
RQ
T
Delay from CE input to AQ – DQ flip-flops
CEO
F
Toggle frequency (for export control)
TOG
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2.
These items are of interest for Carry Chain applications.
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
www.xilinx.com
Speed Grade
Units
-3
-2
-1
0.33
0.36
0.42
ns, Max
0.37
0.42
0.49
ns, Max
0.38
0.42
0.49
ns, Max
0.43
0.50
0.59
ns, Max
0.39
0.44
0.51
ns, Max
0.33
0.37
0.43
ns, Max
0.30
0.34
0.40
ns, Max
0.36
0.42
0.50
ns, Max
0.26
0.30
0.37
ns, Max
0.20
0.22
0.26
ns, Max
0.20
0.22
0.26
ns, Max
0.09
0.10
0.11
ns, Max
0.24
0.27
0.31
ns, Max
0.27
0.30
0.35
ns, Max
0.29
0.32
0.36
ns, Max
0.31
0.35
0.41
ns, Max
0.35
0.40
0.47
ns, Max
0.36
0.41
0.49
ns, Min
0.19
0.21
0.24
0.37
0.42
0.51
ns, Min
0.18
0.20
0.23
ns, Min
–0.04
–0.04
–0.04
0.41
0.49
0.59
ns, Min
–0.19
–0.19
–0.19
0.14
0.16
0.18
ns, Min
0.14
0.16
0.19
0.90
0.90
0.90
ns, Min
0.74
0.86
1.03
ns, Max
0.46
0.52
0.63
ns, Max
1412
1265
1098
MHz
45