FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Table 69: DSP48E Switching Characteristics (Cont’d)
Symbol
TDSPCCK_CEMM/TDSPCKC_CEMM
TDSPCCK_CEPP/TDSPCKC_CEPP
Setup and Hold Times of the RST Pins
TDSPCCK_{RSTAA, RSTBB}/
TDSPCKC_{RSTAA, RSTBB}
TDSPCCK_RSTCC/ TDSPCKC_RSTCC
TDSPCCK_RSTMM/ TDSPCKC_RSTMM
TDSPCCK_RSTPP/TDSPCKC_RSTPP
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_M
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_NM
TDSPDO_{CP, CCRYOUT, CRYINP, CRYINCRYOUT}
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{AACOUT, BBCOUT}
TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT,
BPCOUT, BCRYCOUT, BMULTSIGNOUT}_M
TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT,
BPCOUT, BCRYCOUT, BMULTSIGNOUT}_NM
TDSPDO_{CPCOUT, CCRYCOUT, CMULTSIGNOUT,
CRYINPCOUT, CRYINCRYCOUT,
CRYINMULTSIGNOUT}
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_{ACINP, ACINCRYOUT, BCINP,
BCINCRYOUT}_M
TDSPDO_{ACINP, ACINCRYOUT, BCINP,
BCINCRYOUT}_NM
TDSPDO_{ACINACOUT, BCINBCOUT}
TDSPDO_{ACINPCOUT, ACINCRYCOUT,
ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT,
BCINMULTSIGNOUT}_M
TDSPDO_{ACINPCOUT, ACINCRYCOUT,
ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT,
BCINMULTSIGNOUT}_NM
TDSPDO_{PCINP, CRYCINP, MULTSIGNINP,
PCINCRYOUT, CRYCINCRYOUT,
MULTSIGNINCRYOUT}
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
CEM input to M register CLK
CEP input to P register CLK
{RSTA, RSTB} input to {A, B} register
CLK
RSTC input to C register CLK
RSTM input to M register CLK
RSTP input to P register CLK
{A, B} input to {P, CARRYOUT} output
using multiplier
{A, B} input to {P, CARRYOUT} output
not using multiplier
{C, CARRYIN} input to
{P, CARRYOUT} output
{A, B} input to
{ACOUT, BCOUT} output
{A, B} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
{A, B} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output not using multiplier
{C, CARRYIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output
{ACIN, BCIN} input to {P, CARRYOUT}
output using multiplier
{ACIN, BCIN} input to {P, CARRYOUT}
output not using multiplier
{ACIN, BCIN} input to {ACOUT, BCOUT}
output
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output not using multiplier
{PCIN, CARRYCASCIN, MULTSIGNIN}
input to {P, CARRYOUT} output
www.xilinx.com
Speed
Units
-3
-2
-1
0.25
0.29
0.36
ns
0.18
0.21
0.26
0.56
0.63
0.73
ns
0.01
0.01
0.01
0.24
0.28
0.33
ns
0.23
0.26
0.31
0.19
0.21
0.26
ns
0.17
0.21
0.28
0.25
0.29
0.36
ns
0.18
0.21
0.26
0.56
0.63
0.73
ns
0.01
0.01
0.01
2.78
3.22
3.84
ns
1.59
1.77
2.22
ns
1.50
1.67
2.08
ns
1.00
1.12
1.31
ns
2.78
3.22
3.84
ns
1.72
1.92
2.42
ns
1.63
1.82
2.28
ns
2.78
3.22
3.84
ns
1.59
1.77
2.22
ns
1.00
1.12
1.31
ns
2.78
3.22
3.84
ns
1.72
1.92
2.42
ns
1.30
1.45
1.82
ns
49