FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Page 58/91

Download datasheet (3Mb)Embed
PrevNext
Table 77: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode
Symbol
Outputs Clocks (Low Frequency Mode)
F
1XMRMIN
F
1XMRMAX
F
2XMRMIN
F
2XMRMAX
F
DLLMRMIN
F
DLLMRMAX
F
FXMRMIN
F
FXMRMAX
Input Clocks (Low Frequency Mode)
F
CLKINDLLMRMIN
F
CLKINDLLMRMAX
F
CLKINFXMRMIN
F
CLKINFXMRMAX
F
PSCLKMRMIN
F
PSCLKMRMAX
Notes:
1.
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3.
When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input
frequency.
4.
When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55
to 55/45).
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
(1, 3, 4)
CLKIN (using DLL outputs)
(2, 3, 4)
CLKIN (using DFS outputs only)
PSCLK
www.xilinx.com
Speed Grade
Units
-3
-2
-1
19.00
19.00
19.00
MHz
32.00
32.00
32.00
MHz
38.00
38.00
38.00
MHz
64.00
64.00
64.00
MHz
1.19
1.19
1.19
MHz
21.34
21.34
21.34
MHz
19.00
19.00
19.00
MHz
40.00
40.00
40.00
MHz
19.00
19.00
19.00
MHz
32.00
32.00
32.00
MHz
1.00
1.00
1.00
MHz
40.00
40.00
40.00
MHz
1.00
1.00
1.00
KHz
300.00
270.00
240.00
MHz
58