FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Output Clock Jitter
Table 79: Output Clock Jitter
Symbol
Clock Synthesis Period Jitter
T
PERJITT_0
T
PERJITT_90
T
PERJITT_180
T
PERJITT_270
T
PERJITT_2X
T
PERJITT_DV1
T
PERJITT_DV2
T
PERJITT_FX
Notes:
1.
Values for this parameter are available in the Architecture Wizard.
Output Clock Phase Alignment
Table 80: Output Clock Phase Alignment
Symbol
Phase Offset Between CLKIN and CLKFB
T
CLKIN/CLKFB
IN_FB_OFFSET
Phase Offset Between Any DCM Outputs
T
CLK0, CLK90, CLK180, CLK270
OUT_OFFSET_1X
T
CLK2X, CLK2X180, CLKDV
OUT_OFFSET_2X
T
CLKFX, CLKFX180
OUT_OFFSET_FX
(2)
Duty Cycle Precision
T
DLL outputs
DUTY_CYC_DLL
T
DFS outputs
DUTY_CYC_FX
Notes:
1.
All phase offsets are in respect to group CLK1X.
2.
CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION = TRUE. The duty cycle distortion includes the global clock tree (BUFG).
3.
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
4.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
Constraints
CLK0
CLK90
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
Description
Constraints
(1)
(3)
(4)
www.xilinx.com
Speed Grade
Units
-3
-2
-1
±120
±120
±120
ps
±120
±120
±120
ps
±120
±120
±120
ps
±120
±120
±120
ps
±200
±200
±230
ps
±150
±150
±180
ps
±300
±300
±345
ps
Note 1
Note 1
Note 1
ps
Speed Grade
Units
-3
-2
-1
±50
±50
±60
ps
±140
±140
±160
ps
±150
±150
±200
ps
±160
±160
±220
ps
±150
±150
±180
ps
±150
±150
±180
ps
60