FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Table 81: Miscellaneous Timing Parameters
Symbol
Time Required to Achieve LOCK
T
DLL output – Frequency range > 240 MHz
DLL_240
T
DLL output – Frequency range 120 - 240 MHz
DLL_120_240
T
DLL output – Frequency range 60 - 120 MHz
DLL_60_120
T
DLL output – Frequency range 50 - 60 MHz
DLL_50_60
T
DLL output – Frequency range 40 - 50 MHz
DLL_40_50
T
DLL output – Frequency range 30 - 40 MHz
DLL_30_40
T
DLL output – Frequency range 24 - 30 MHz
DLL_24_30
T
DLL output – Frequency range < 30 MHz
DLL_30
T
DFS outputs
FX_MIN
T
FX_MAX
T
Multiplication factor for DLL lock time with Fine Shift
DLL_FINE_SHIFT
Fine Phase Shifting
T
Absolute shifting range in maximum speed mode
RANGE_MS
T
Absolute shifting range in maximum range mode
RANGE_MR
Delay Lines
T
Tap delay resolution (Min) in maximum speed mode
TAP_MS_MIN
T
Tap delay resolution (Max) in maximum speed mode
TAP_MS_MAX
T
Tap delay resolution (Min) in maximum range mode
TAP_MR_MIN
T
Tap delay resolution (Max) in maximum range mode
TAP_MR_MAX
Notes:
1.
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
Table 82: Frequency Synthesis
Attribute
CLKFX_MULTIPLY
CLKFX_DIVIDE
Table 83: DCM Switching Characteristics
Symbol
T
/ T
DMCCK_PSEN
DMCKC_PSEN
T
/ T
DMCCK_PSINCDEC
DMCKC_PSINCDEC
T
DMCKO_PSDONE
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
Min
2
1
Description
PSEN Setup/Hold
PSINCDEC Setup/Hold
Clock to out of PSDONE
www.xilinx.com
Speed Grade
-3
-2
-1
Units
80.00
80.00
80.00
µs
250.00
250.00
250.00
µs
900.00
900.00
900.00
µs
1300.00
1300.00
1300.00
µs
2000.00
2000.00
2000.00
µs
3600.00
3600.00
3600.00
µs
5000.00
5000.00
5000.00
µs
5000.00
5000.00
5000.00
µs
10.00
10.00
10.00
ms
10.00
10.00
10.00
ms
2.00
2.00
2.00
7.00
7.00
7.00
ns
10.00
10.00
10.00
ns
7.00
7.00
7.00
ps
30.00
30.00
30.00
ps
10.00
10.00
10.00
ps
40.00
40.00
40.00
ps
Max
33
32
Speed Grade
Units
-3
-2
-1
1.20
1.35
1.56
ns
0.00
0.00
0.00
1.20
1.35
1.56
ns
0.00
0.00
0.00
1.00
1.12
1.30
ns
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