FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-5 FPGA
source-synchronous transmitter and receiver data-valid windows.
Table 98: Duty Cycle Distortion and Clock-Tree Skew
Symbol
T
Global Clock Tree Duty Cycle Distortion
DCD_CLK
T
Global Clock Tree Skew
CKSKEW
T
I/O clock tree duty cycle distortion
DCD_BUFIO
T
I/O clock tree skew across one clock region
BUFIOSKEW
T
Regional clock tree duty cycle distortion
DCD_BUFR
Notes:
1.
These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
2.
The T
value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
CKSKEW
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to the application.
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
Device
(1)
(2)
XC5VLX20T
XC5VLX30
XC5VLX30T
XC5VLX50
XC5VLX50T
XC5VLX85
XC5VLX85T
XC5VLX110
XC5VLX110T
XC5VLX155
XC5VLX155T
XC5VLX220
XC5VLX220T
XC5VLX330
XC5VLX330T
XC5VSX35T
XC5VSX50T
XC5VSX95T
XC5VSX240T
XC5VTX150T
XC5VTX240T
XC5VFX30T
XC5VFX70T
XC5VFX100T
XC5VFX130T
XC5VFX200T
www.xilinx.com
Speed Grade
-3
-2
-1
All
0.12
0.12
0.12
N/A
0.24
0.25
0.21
0.22
0.22
0.21
0.22
0.22
0.26
0.27
0.28
0.26
0.27
0.28
0.42
0.43
0.45
0.42
0.43
0.45
0.48
0.50
0.51
0.48
0.50
0.51
0.82
0.85
0.88
0.82
0.85
0.88
N/A
1.07
1.10
N/A
1.07
1.10
N/A
1.25
1.29
N/A
1.25
1.29
0.38
0.39
0.39
0.43
0.44
0.45
N/A
0.72
0.74
N/A
1.32
1.36
N/A
0.70
0.73
N/A
0.97
1.00
0.34
0.35
0.35
0.41
0.42
0.43
0.82
0.84
0.86
0.82
0.84
0.86
N/A
1.24
1.29
All
0.10
0.10
0.10
All
0.07
0.07
0.08
All
0.25
0.25
0.25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
83