MCP3903T-E/SS Microchip Technology, MCP3903T-E/SS Datasheet
MCP3903T-E/SS
Specifications of MCP3903T-E/SS
Related parts for MCP3903T-E/SS
MCP3903T-E/SS Summary of contents
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... Extended Temperature Range: -40°C to +125°C Applications • Energy Metering and Power Measurement • Portable Instrumentation • Medical and Power Monitoring © 2011 Microchip Technology Inc. MCP3903 Description The MCP3903 is a six-channel Analog Front End (AFE) containing three pairs made out of two synchronous ...
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... Modulator Phase PHASEC <7:0> Φ Shifter DATA_CH5<23:0> 3 Δ -Σ SINC Modulator POR AGND DGND Xtal Oscillator OSC1 MCLK Clock Generation OSC2 OSR<1:0> DMCLK PRE<1:0> DRA DRB Digital SPI Interface DRC SDO RESET SDI SCK CS © 2011 Microchip Technology Inc. ...
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... For proper operation and to keep ADC accuracy, AMCLK should always be in the range MHz with BOOST bits off. With BOOST bits on, AMCLK should be in the range 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a crystal, CLKEXT bit should be equal to ‘0’. © 2011 Microchip Technology Inc. 1.1 RELIABILITY TARGETS ABSOLUTE MAXIMUM RATINGS † ...
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... From -40°C to 125°C All Gains GAIN = 1, DITHER = ON Proportional to 1/AMCLK T = 25°C OSR = 256, DITHER = ON; (Note 2)(Note 25°C OSR = 256, DITHER = ON; (Note 2) (Note 3) OSR = 256, DITHER = ON; (Note 2)(Note 1Vpp @ 4.5 to 5.5V 3.3V V varies from -1V to +1V; CM (Note 2) © 2011 Microchip Technology Inc. ...
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... For proper operation and to keep ADC accuracy, AMCLK should always be in the range MHz with BOOST bits off. With BOOST bits on, AMCLK should be in the range 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a crystal, CLKEXT bit should be equal to ‘0’. © 2011 Microchip Technology Inc. (CONTINUED MHz ...
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... SDO pin only mA 3. DRn pins only +1.5 mA, DV =3. SDO pin only mA 3. DRn pins only -1.5 mA, DV =3. µ Inputs tied DGND DD OR µ Inputs tied DGND 25°C, SCK = 1.0 MHz 3.3V (Note 1) DD © 2011 Microchip Technology Inc. ...
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... Serial Output Timing Diagram CSS Mode 1,1 Mode 0,0 SCK SDI MSB in SDO FIGURE 1-2: Serial Input Timing Diagram. © 2011 Microchip Technology Inc. Min Typ Max -40 — +125 A -65 — +150 A — 71 — must not exceed the absolute maximum specification of +150°C. ...
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... MCP3903 Clock Detail. DS25048B-page DRCLK Timing Waveform for SDO t DOMDAT PRESCALE<1:0> Prescale MCLK AMCLK Clock Divider Clock Divider t DRP DIS V IH 90% t HI-Z DIS 10% OSR<1:0> f ADC f ADC D S Output Sampling Data Rate Rate 1 / OSR DMCLK DRCLK Clock Divider © 2011 Microchip Technology Inc. ...
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... Note: Unless otherwise indicated OSR = 64; GAIN = 1; Dithering OFF FIGURE 2-1: Spectral Response. FIGURE 2-2: Spectral Response. FIGURE 2-3: Spectral Response. © 2011 Microchip Technology Inc. = 5.0V 3.3 V; Internal REF A = -0.5 dBFS @ 60 Hz. IN FIGURE 2-4: FIGURE 2-5: ...
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... OSR = 256 OSR = 256 OSR = 256 OSR = 256 OSR = 256 OSR = 256 OSR = 128 OSR = 128 OSR = 128 OSR = 128 OSR = 128 OSR = 64 OSR = 64 OSR = 64 OSR = 64 OSR = 32 OSR = 32 OSR = GAIN (V/V) Signal-to-Noise and Total Harmonic Distortion © 2011 Microchip Technology Inc. ...
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... Input Frequency (Hz) Input Frequency (Hz) FIGURE 2-15: Signal-to-Noise and Distortion vs. Input Signal Frequency. © 2011 Microchip Technology Inc. = 5.0V 3 +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = DD A 120 120 120 120 120 120 120 fs=15.625KHz fs=15.625KHz fs=15.625KHz fs=15 ...
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... FIGURE 2-23: vs. Supply Voltage 105 125 105 125 FIGURE 2-24: -40 -40 -20 - 105 125 105 125 Temperature (°C) Temperature (°C) Internal Voltage Reference 5 5 5.5 5.5 Power Supply (V) Power Supply (V) Internal Voltage Reference Noise Histogram. © 2011 Microchip Technology Inc. ...
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... DIDD DIDD DIDD MCLK Frequency(MHz) MCLK Frequency(MHz) FIGURE 2-27: Operating Current vs. Master Clock (MCLK). © 2011 Microchip Technology Inc. = 5.0V 3 +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = DD A CH0 CH0 CH0 CH0 CH0 CH0 CH0 0.25 0.25 0.5 0.5 0.25 0.25 0.5 ...
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... RESET rising edge. This input is Schmitt triggered. 3.2 Digital V ( the power supply pin for the digital circuitry DD within the MCP3903. This pin requires appropriate bypass capacitors and should be maintained between 2.7V and 3.6V for specified operation. © 2011 Microchip Technology Inc. ...
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... For optimal performance, bypass capacitances should be connected between this pin and AGND at all times even when the internal voltage reference is used. © 2011 Microchip Technology Inc. MCP3903 3.7 Inverting Reference Input (REFIN-) This pin is the inverting side of the differential voltage reference input for both ADCs ...
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... SDI pin. Each write is processed by packets of 24 bits (size of each register). Each command is either a Read or a Write command. Toggling SDI during a Read command has no effect. This input is Schmitt-triggered. © 2011 Microchip Technology Inc. ...
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... This is the fastest clock present in the device. This is the frequency of the crystal placed at the OSC1/OSC2 inputs when CLKEXT = 0 or the frequency of the clock input at the OSC1/CLKI when CLKEXT = 1. © 2011 Microchip Technology Inc. MCP3903 4.2 AMCLK - Analog Master Clock This is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the CONFIG PRESCALE< ...
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... MCLK/1024 3.9 MCLK/4096 0.976 MCLK/2048 1.95 MCLK/1024 3.9 MCLK/512 7.8125 MCLK/2048 1.95 MCLK/1024 3.9 MCLK/512 7.8125 MCLK/256 15.625 MCLK/1024 3.9 MCLK/512 7.8125 MCLK/256 15.625 MCLK/128 31.25 = 0V). The specification IN Section 2.0 “Typical Performance REF ).This REF © 2011 Microchip Technology Inc. ...
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... SINAD log 10 + © 2011 Microchip Technology Inc. 4.11 Total Harmonic Distortion (THD) The total harmonic distortion is the ratio of the output harmonics power to the fundamental signal power for a sinewave input and is defined by the following equation. EQUATION 4-7: ( THD dB The THD calculation includes the first 35 harmonics for the MCP3903 specifications ...
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... SINAD, THD, SFDR) are less signal dependent. The MCP3903 incorporates a proprietary dithering algorithm on all ADCs in order to remove idle tones and improve THD, which is crucial for power metering applications. © 2011 Microchip Technology Inc. ...
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... DC values (the power supply is a sinewave at a certain frequency with a certain common mode). In AC, the amplitude of the sinewave is representing the change in the power supply defined as: © 2011 Microchip Technology Inc. EQUATION 4-11: PSRR dB Where V is the equivalent input voltage that the ...
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... MCLK edge coming while in this mode will induce dynamic power consumption. Once any of the SHUTDOWN, CLKEXT and VREFEXT bits returns to 0, the POR AV back to operation and AV and POR VDD monitoring block is DD monitoring can take place. DD © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. 5.3 Delta-Sigma Modulator 5.3.1 ARCHITECTURE All ADCs are identical in the MCP3903 and they include a second-order modulator with a multi-bit DAC architecture (see ADC composed of 4 comparators with equally spaced thresholds and a thermometer output coding. The proprietary 5-level architecture ensures minimum ...
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... MHz while keeping the ADC accuracy. When disabled, the power consumption returns back to normal and the AMCLK clock frequencies can only reach MHz without affecting ADC accuracy. DS25048B-page 24 and scales REF /3 since REF include an © 2011 Microchip Technology Inc. ...
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... OSR 1 z – Where: ⎛ ⎞ 2π exp --------------------- - ⎝ ⎠ DMCLK © 2011 Microchip Technology Inc. The Normal-Mode Rejection Ratio (NMRR), or gain of the transfer function, is shown in the following equation: EQUATION 5-2: NMRR or: ADC Resolution NMRR (bits) No Missing Codes 17 where ...
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... Equation 5-1 5-2). (For 24-bit Mode Or WIDTH_CHn = 1) (For 16-bit Mode Or WIDTH_CHn = 0) Hexadecimal Decimal 0x7FFFFF + 8,388,607 0x7FFFFE + 8,388,606 0x000000 0 0xFFFFFF -1 0x800001 - 8,388,607 0x800000 - 8,388,608 Decimal Hexadecimal 23-bit Resolution 0x7FFFFE + 4,194,303 0x7FFFFC + 4,194,302 0x000000 0 0xFFFFFE -1 0x800002 - 4,194,303 0x800000 - 4,194,304 © 2011 Microchip Technology Inc. ...
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... REFIN+/OUT and AGND. De-coupling at the sampling frequency, around 1 MHz, is important for any noise around this frequency will be aliased back into the conversion data. 0.1 µF ceramic and 10 µF tantalum capacitors are recommended. © 2011 Microchip Technology Inc. Hexadecimal ...
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... Typically, the time difference between the data ready pulses of channel 0 and channel 1 is equal to the phase delay setting. A detailed explanation of the Data Ready Note: pins (DRn) with phase delay is present in Section 6.10 (DRn)”. Phase Register Code = ------------------------------------------------- - DMCLK “Data Ready Pulses © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. 5.10 Crystal Oscillator The MCP3903 includes a Pierce-type crystal oscillator with very high stability and ensures very low tempco and jitter for the clock generation. This oscillator can handle up to 16.384 MHz crystal frequencies, provided that proper load capacitances and quartz quality factor are used ...
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... SPI MODE 0,0 - Clock Idle Low, Read/Write Examples In this SPI mode, the clock idles low. For the MCP3903, this means that there will be a rising edge before there is a falling edge. R/W Read Write Bit 6.6 © 2011 Microchip Technology Inc. ...
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... DATA TRANSITIONS ON THE FALLING EDGE MCU AND MCP3901 LATCH BITS ON THE RISING EDGE SCK 1 SDI HI-Z HI-Z SDO FIGURE 6-4: Device Read (SPI Mode 1,1 - Clock Idles High). © 2011 Microchip Technology Inc. R/W D23 D15 D07 06 (ADDRESS) 24 BIT DATA . A0 R/W ...
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... WIDTH=0). The following figure represents a typical continuous read communication with the default settings (DRMODE<1:0>=00, READ<1:0>=10) for both WIDTH settings. This configuration is typically used for power metering applications. CH5 CH5 HI-Z CH5 CH5 5 © 2011 Microchip Technology Inc. ...
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... Overwrite of identical PHASE register value 5: Change in EXTCLK bit in the CONFIG register modifying internal oscillator state. © 2011 Microchip Technology Inc. MCP3903 After these temporary resets, the ADCs go back to normal operation with no need for an additional command. These are also the settings where the DR position is affected ...
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... If DRn_MODE<1:0>=11, the user will still Note: be able to retrieve the data ready pulse for the ADC not in shutdown or reset, i.e. only 1 ADC channel needs to be awake. set with the applications, (default be no data ready pulses if © 2011 Microchip Technology Inc. ...
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... PHASE < 0 FIGURE 6-8: Data Ready Behavior. © 2011 Microchip Technology Inc. PHASE = 0 PHASE > 0 MCP3903 DS25048B-page 35 ...
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... TYPES is recommended (READ<1:0>=10) so that all data can be latched once at the beginning of the read. In the read mode by GROUP (READ<1:0>=01) mode, the data will be relatched every time the part accesses to each group or pair of ADCs. © 2011 Microchip Technology Inc. ...
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... MOD 0x06 PHASE 0x07 GAIN 0x08 STATUS/ 0x09 COM CONFIG 0x0A © 2011 Microchip Technology Inc Channel 0 ADC Data <23:0>, MSB first, left justified 24 R Channel 1 ADC Data <23:0>, MSB first, left justified 24 R Channel 2 ADC Data <23:0>, MSB first, left justified ...
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... ADC output data of the corresponding channel DS25048B-page 38 R-0 R-0 R-0 D20 D19 D18 R-0 R-0 R-0 D12 D11 D10 R-0 R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. R-0 R-0 D17 D16 bit 16 R-0 R bit 8 R-0 R bit Bit is unknown ...
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... COMPn_CH1: Comparator Outputs from ADC Channel 1 bit 3:0 COMPn_CH0: Comparator Outputs from ADC Channel 0 © 2011 Microchip Technology Inc. The MOD register contains the most recent modulator data output. The default value corresponds to an equivalent input each ADC. Each bit in this register corresponds to one comparator output on one of the channels ...
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... R/W-0 PHASEB4 PHASEB3 PHASEB2 R/W-0 R/W-0 R/W-0 PHASEA4 PHASEA3 PHASEA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 PHASEC1 PHASEC0 bit 16 R/W-0 R/W-0 PHASEB1 PHASEB0 bit 8 R/W-0 R/W-0 PHASEA1 PHASEA0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... Gain is 8 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 bit BOOST_CHn Current Scaling for high speed operation for channel Channel has current Channel has normal current © 2011 Microchip Technology Inc. Cof R/W R/W-0 R/W-0 R/W-0 BOOST_ CH5 BOOST_ CH4 ...
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... MCU I/O. R/W-0 R/W-0 R/W-0 WIDTH_CH5 WIDTH_CH4 WIDTH_CH3 R/W-0 R/W-0 R/W-0 DR_LINK DRC_MODE1 DRC_MODE0 R-1 R-1 R-1 the same DRn output pin R/W-0 R/W-0 WIDTH_CH2 WIDTH_CH1 bit 16 R/W-0 R/W-0 DRB_MODE1 DRB_MODE0 bit 8 R-1 R-1 bit 0 © 2011 Microchip Technology Inc. ...
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... Data Ready pulses from the lagging ADC channel between the two are output on DRA pin. The lagging ADC channel depends on the phase register and on the OSR. (DEFAULT) bit 5:0 DRSTATUS_CHn: Data Ready Status 1 = Data Not Ready (default Data Ready © 2011 Microchip Technology Inc. MCP3903 DS25048B-page 43 ...
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... XT Mode - A crystal must be placed between OSC1/OSC2 (default) DS25048B-page 44 Cof R/W R/W-0 R/W-0 R/W-0 RESET_CH2 RESET_CH1 RESET_CH0 SHUTDOWN_CH5 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 OSR0 PRESCALE1 PRESCALE0 R/W-0 R/W-0 SHUTDOWN_CH4 bit 16 R/W-1 R/W-1 DITHER_CH3 DITHER_CH2 bit 8 R/W-0 R/W-0 EXTVREF EXTCLK bit © 2011 Microchip Technology Inc. ...
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... In the event the full Microchip part number cannot be marked on one line, it will Note: be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011 Microchip Technology Inc. MCP3903 Example MCP3903 E/SS ...
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... MCP3903 /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± PP %RG\ >6623@ 1RWH NOTE 1RWHV DS25048B-page © 2011 Microchip Technology Inc. φ L ...
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... Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc. MCP3903 DS25048B-page 47 ...
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... MCP3903 DS25048B-page 48 © 2011 Microchip Technology Inc. ...
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... APPENDIX A: REVISION HISTORY Revision B (July 2011) • Added Section 2.0, Typical Performance Curves, with characterization graphs. Revision A (June 2011) • Original data sheet for the MCP3903 device. © 2011 Microchip Technology Inc. MCP3903 DS25048B-page 51 ...
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... MCP3903 NOTES: DS25048B-page 52 © 2011 Microchip Technology Inc. ...
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... Package Small Shrink Output Package (SSOP-28) © 2011 Microchip Technology Inc. X /XX Examples: a) Package Range b) MCP3903 . MCP3903T-E/SS: Tape and Reel, Six Channel ΔΣ A/D Converter, SSOP-28 package MCP3903T-I/SS: Tape and Reel, Six Channel ΔΣ A/D Converter, SSOP-28 package DS25048B-page 53 ...
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... MCP3903 NOTES: DS25048B-page 54 © 2011 Microchip Technology Inc. ...
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... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2011 Microchip Technology Inc. 05/02/11 ...