PIC12F1822-E/MF Microchip Technology, PIC12F1822-E/MF Datasheet

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PIC12F1822-E/MF

Manufacturer Part Number
PIC12F1822-E/MF
Description
3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 D
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheets

Specifications of PIC12F1822-E/MF

Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-DFN
Processor Series
PIC12F
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC12F/LF1822/PIC16F/LF1823
Data Sheet
8/14-Pin Flash Microcontrollers
with nanoWatt XLP Technology
Preliminary
 2010 Microchip Technology Inc.
DS41413B

Related parts for PIC12F1822-E/MF

PIC12F1822-E/MF Summary of contents

Page 1

... PIC12F/LF1822/PIC16F/LF1823  2010 Microchip Technology Inc. 8/14-Pin Flash Microcontrollers with nanoWatt XLP Technology Preliminary Data Sheet DS41413B ...

Page 2

... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... Reference Clock module: - Programmable clock output frequency and duty-cycle Special Microcontroller Features: • Full 5.5V Operation – PIC12F1822/16F1823 • 1.8V-3.6V Operation – PIC12LF1822/16LF1823 • Self-Reprogrammable under Software Control • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • ...

Page 4

... Data Signal Modulator module - Selectable modulator and carrier sources • SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications PIC12F/LF1822/16F/LF1823 Family Types Program Data Memory Memory PIC12LF1822 2K 128 PIC12F1822 2K 128 PIC16LF1823 2K 128 PIC16F1823 2K 128 One pin is input only. Note 1: DS41413B-page 4 256 ...

Page 5

FIGURE 1: 8-PIN DIAGRAM FOR PIC12F/LF1822 PDIP, SOIC, DFN (1) (1) (1) (1) RX /DT /CCP1 /P1A /SRNQ/T1CKI/T1OSI/OSC1/CLKIN/RA5 (1) (1) (1) (1) (1) MDCIN2/T1G /P1B /TX /CK /SDO /CLKR/C1IN1-/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 Pin function is selectable via the APFCON register. Note 1: TABLE ...

Page 6

FIGURE 2: 14-PIN DIAGRAM FOR PIC16F/LF1823 PDIP, SOIC, TSSOP T1CKI/T1OSI/OSC1/CLKIN/RA5 (1) (1) T1G /SDO /CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 MCLR/V MDCIN2/RX (1) /DT (1) (1) MDOUT/TX /CK /P1B/SRNQ/C2OUT/RC4 MDMIN/SS (1) /P1C/C12IN3-/CPS7/AN7/RC3 Note 1: Pin function is selectable via the APFCON register ...

Page 7

FIGURE 3: 14-PIN DIAGRAM FOR PIC16F/LF1823 QFN T1CKI/T1OSI/OSC1/CLKIN/RA5 (1) (1) T1G /SDO /CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 (1) MCLR/V /T1G /SS PP MDCIN2/RX (1) /DT (1) /CCP1/P1A/RC5 Note 1: Pin function is selectable via the APFCON register PIC16F/LF1823 (1) /RA3 ...

Page 8

... OSC1 CLKIN SCL — — Y — SCK SDA — — Y — SDI (1) SDO — MDCIN1 Y — (1) SS — MDMIN Y — — — MDOUT Y — — — MDCIN2 Y — — — — — — — — —  2010 Microchip Technology Inc. ...

Page 9

... Packaging Information.............................................................................................................................................................. 379 Appendix A: Revision History............................................................................................................................................................. 393 Appendix B: Device Differences ........................................................................................................................................................ 393 Index .................................................................................................................................................................................................. 395 The Microchip Web Site ..................................................................................................................................................................... 401 Customer Change Notification Service .............................................................................................................................................. 401 Customer Support .............................................................................................................................................................................. 401 Reader Response .............................................................................................................................................................................. 402 Product Identification System ............................................................................................................................................................ 403  2010 Microchip Technology Inc. ) ................................................................................................................................ 323 ™ Preliminary DS41413B-page 9 ...

Page 10

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS41413B-page 10 to receive the most current information on all of our products. Preliminary  2010 Microchip Technology Inc. ...

Page 11

... Digital Signal Modulator (DSM) EUSART Fixed Voltage Reference (FVR) SR Latch Capture/Compare/PWM Modules ECCP1 Comparators C1 C2 Master Synchronous Serial Ports MSSP Timers Timer0 Timer1 Timer2  2010 Microchip Technology Inc. of the 1-2 and 1-3 ● ● ● ● ● ● ● ● ● ...

Page 12

... See applicable chapters for more information on peripherals. Note 1: See Table 1-1 for peripherals available on specific devices. 2: PIC16F/LF1823 only. 3: DS41413B-page 12 Program Flash Memory RAM CPU (Figure 2-1) ADC Timer1 DAC Comparators 10-Bit Modulator FVR EUSART CapSense Preliminary EEPROM PORTA (3) PORTC  2010 Microchip Technology Inc. ...

Page 13

... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Pin functions can be assigned to one of two pin locations via software. See APFCON register Note 1:  2010 Microchip Technology Inc. Input Output Type Type TTL CMOS General purpose I/O. ...

Page 14

... CMOS USART synchronous data. ST — USART asynchronous input. Power — Positive supply. Power — Ground reference. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels (Register 12-1).  2010 Microchip Technology Inc. ...

Page 15

... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Pin functions can be assigned to one of two pin locations via software. See APFCON register Note 1:  2010 Microchip Technology Inc. Input Output Type Type TTL CMOS General purpose I/O. ...

Page 16

... CMOS PWM output. ST CMOS Capture/Compare/PWM 1. ST CMOS USART synchronous data. ST — USART asynchronous input. ST — Modulator Carrier Input 2. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels (Register 12-1).  2010 Microchip Technology Inc. ...

Page 17

... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Pin functions can be assigned to one of two pin locations via software. See APFCON register Note 1:  2010 Microchip Technology Inc. Input Output Type Type Power — ...

Page 18

... PIC12F/LF1822/PIC16F/LF1823 NOTES: DS41413B-page 18 Preliminary  2010 Microchip Technology Inc. ...

Page 19

... Section 3.5 “Indirect Addressing” 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 “Instruction Set Summary” details.  2010 Microchip Technology Inc. Saving”, for more for more Preliminary DS41413B-page 19 ...

Page 20

... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W Reg Timer Brown-out Reset Preliminary RAM Addr 12 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX  2010 Microchip Technology Inc. ...

Page 21

... Section 11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC12F/LF1822/PIC16F/LF1823  2010 Microchip Technology Inc. The following features are associated with access and control of program memory and data memory: memory in • PCL and PCLATH • Stack (1) ...

Page 22

... If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 7FFFh Preliminary Example 3-1. RETLW INSTRUCTION ;Add Index ;program counter to ;select data ;Index0 data ;Index1 data DATA_INDEX  2010 Microchip Technology Inc. ...

Page 23

... File Select Registers (FSR). See Section 3.5 for more information. Addressing”  2010 Microchip Technology Inc. 3.2.1 CORE REGISTERS The core registers contain the registers that directly affect the basic PIC12F/LF1822/16F/LF1823. These registers are listed below: • ...

Page 24

... Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. R-1/q R-1/q R/W-0 Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) Preliminary Section 29.0 Summary”). R/W-0/u R/W-0/u (1) ( bit 0  2010 Microchip Technology Inc. ...

Page 25

... General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) 7Fh  2010 Microchip Technology Inc. 3.2.5 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: Device PIC12F/LF1822/16F/LF1823 Section 3.5.2 ...

Page 26

TABLE 3-3: PIC12F/LF1822/PIC16F/LF1823 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H ...

Page 27

TABLE 3-4: PIC12F/LF1822/16F/LF1823 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 INDF0 400h 480h 500h INDF1 INDF1 401h 481h 501h PCL PCL 402h 482h 502h STATUS STATUS 403h 483h 503h FSR0L FSR0L 404h 484h 504h FSR0H FSR0H 405h 485h ...

Page 28

TABLE 3-5: PIC12F/LF1822/16F/LF1823 MEMORY MAP, BANKS 16-23 BANK 16 BANK 17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H ...

Page 29

TABLE 3-6: PIC12F/LF1822/16F/LF1823 MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H ...

Page 30

... STKPTR FEEh TOSL FEFh TOSH = Unimplemented data memory locations, Legend: read as ‘0’. DS41413B-page 30 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device PIC12F/LF1822/PIC16F/LF1 823 Preliminary  2010 Microchip Technology Inc. Bank(s) Page No ...

Page 31

... CPSCON1 — — unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC16F/LF1823 only.  2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — — BSR<4:0> ...

Page 32

... SWDTEN --01 0110 --01 0110 --00 0000 --00 0000 SCS<1:0> 0011 1-00 0011 1-00 LFIOFR HFIOFS 10q0 0q00 qqqq qq0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GO/DONE ADON -000 0000 -000 0000 ADPREF<1:0> 0000 --00 0000 --00 — —  2010 Microchip Technology Inc. ...

Page 33

... Unimplemented 11Fh — Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC16F/LF1823 only.  2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — — BSR<4:0> ...

Page 34

... OERR RX9D 0000 000x 0000 000x TRMT TX9D 0000 0010 0000 0010 WUE ABDEN 01-0 0-00 01-0 0-00  2010 Microchip Technology Inc. ...

Page 35

... Unimplemented 21Fh — Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC16F/LF1823 only.  2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — — BSR<4:0> ...

Page 36

... PSS1BD<1:0> 0000 0000 0000 0000 STR1B STR1A ---0 0001 ---0 0001 — — — — — — — — — — — — — — — — — —  2010 Microchip Technology Inc. ...

Page 37

... Unimplemented 31Fh — Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC16F/LF1823 only.  2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — — BSR<4:0> ...

Page 38

... CLKRDIV<2:0> 0011 0000 0011 0000 — — — MDBIT 0010 ---0 0010 ---0 x--- xxxx u--- uuuu xxx- xxxx uuu- uuuu xxx- xxxx uuu- uuuu  2010 Microchip Technology Inc. ...

Page 39

... Unimplemented 41Fh — Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC16F/LF1823 only.  2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — — BSR<4:0> ...

Page 40

... INTF IOCIF 0000 000x 0000 000u — —  2010 Microchip Technology Inc. ...

Page 41

... Top-of-Stack High byte TOSH x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC16F/LF1823 only.  2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — — ...

Page 42

... If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will 0 be loaded with the address BRW If using BRA, the entire PC will be loaded with the signed value of the operand of the BRA instruction. 0 BRA Preliminary  2010 Microchip Technology Inc. ...

Page 43

... FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL  2010 Microchip Technology Inc. 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...

Page 44

... Program Counter and pop the stack. 0x09 0x08 0x07 STKPTR = 0x06 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address Preliminary  2010 Microchip Technology Inc. ...

Page 45

... The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory  2010 Microchip Technology Inc. 0x0F Return Address 0x0E Return Address 0x0D ...

Page 46

... Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41413B-page 46 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Preliminary  2010 Microchip Technology Inc. ...

Page 47

... FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2  2010 Microchip Technology Inc. Indirect Addressing 0 7 FSRxH Bank Select 11111 Bank 31 Preliminary 7 ...

Page 48

... FIGURE 3-11: 7 FSRnH 0 1 Location Select 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F 0xF20 Bank 30 0xF6F Preliminary the FSR/INDF interface. All PROGRAM FLASH MEMORY MAP FSRnL 0x8000 0x0000 Program Flash Memory (low 8 bits) 0x7FFF 0xFFFF  2010 Microchip Technology Inc. ...

Page 49

... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 register at 8008h. The DEBUG bit in Configuration Word 2 is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'.  2010 Microchip Technology Inc. by device Preliminary DS41413B-page 49 ...

Page 50

... The entire program memory will be erased when the code protection is turned off. 3: DS41413B-page 50 R/P-1/1 R/P-1/1 R/P-1/1 BOREN<1:0> R/P-1/1 R/P-1/1 R/P-1/1 WDTE<1:0> Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) (3) (1) Preliminary R/P-1/1 R/P-1/1 CPD CP bit 7 R/P-1/1 R/P-1/1 FOSC<2:0> bit 0  2010 Microchip Technology Inc. ...

Page 51

... Enabling Brown-out Reset does not automatically enable Power-up Timer. Note 1: The entire data EEPROM will be erased when the code protection is turned off during an erase. 2: The entire program memory will be erased when the code protection is turned off. 3:  2010 Microchip Technology Inc. Preliminary DS41413B-page 51 ...

Page 52

... R/P-1/1 R/P-1/1 — BORV STVREN R-1 U-1 U-1 — — Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) Preliminary R/P-1/1 U-1 PLLEN — bit 7 R/P-1/1 R/P-1/1 WRT<1:0> bit 0  2010 Microchip Technology Inc. ...

Page 53

... See Section 11.5 “User ID, Device ID and Configuration for more information on accessing these Word Access” memory locations. For more information on checksum calculation, see the “PIC16F/LF1826/27/PIC12F/LF1822 Memory Programming Specification” (DS41390).  2010 Microchip Technology Inc. “Write such as Preliminary DS41413B-page 53 ...

Page 54

... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 13-5 DEV<8:0>: Device ID bits 100111000 = PIC12F1822 100111001 = PIC16F1823 101000000 = PIC12LF1822 101000001 = PIC16LF1823 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. This location cannot be written. ...

Page 55

... XT, HS modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources  2010 Microchip Technology Inc. The oscillator module can be configured in one of eight clock modes. 1. ECL – External Clock Low Power mode (0 MHz to 0 ...

Page 56

... WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules Preliminary Sleep CPU and T1OSC Peripherals Clock Control FOSC<2:0> SCS<1:0> Clock Source Option for other modules  2010 Microchip Technology Inc. ...

Page 57

... High-power, 4-32 MHz (FOSC = 111) • Medium power, 0.5-4 MHz (FOSC = 110) • Low-power, 0-0.5 MHz (FOSC = 101)  2010 Microchip Technology Inc. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...

Page 58

... Preliminary CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic R (3) ( Sleep F OSC2/CLKOUT R S (1) ) may be required for S varies with the Oscillator mode F P Oscillator Start-up Timer (OST) Section 5.4 Mode”). 4X PLL Specifications in Section 30.0  2010 Microchip Technology Inc. ) ...

Page 59

... MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288)  2010 Microchip Technology Inc. 5.2.1.6 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...

Page 60

... OSCSTAT register indicates when the MFINTOSC is running and can be utilized. Preliminary (Register 5-3). Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information. Internal Oscillator Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information.  2010 Microchip Technology Inc. ...

Page 61

... Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized.  2010 Microchip Technology Inc. 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits 5-3) ...

Page 62

... Clock switching time delays are shown in Start-up delay specifications are located in the oscillator tables of Specifications”. Preliminary  2010 Microchip Technology Inc. Figure 5-7). If this is the Table 5-1. Section 30.0 “Electrical ...

Page 63

... IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock  2010 Microchip Technology Inc. Start-up Time 2-cycle Sync 0 2-cycle Sync  LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync  0 Preliminary ...

Page 64

... The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. Start-up or Preliminary Section 21.0 for more  2010 Microchip Technology Inc. ...

Page 65

... LFINTOSC Any clock source Timer1 Oscillator PLL inactive PLL active PLL inactive. Note 1:  2010 Microchip Technology Inc. 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Word Inter- nal/External Switchover bit (Two-Speed Start-up mode enabled). • ...

Page 66

... CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator Preliminary  2010 Microchip Technology Inc. ...

Page 67

... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.  2010 Microchip Technology Inc. 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...

Page 68

... Clock Monitor Output (Q) OSCFIF The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in Note: this example have been chosen for clarity. DS41413B-page 68 Oscillator Failure Test Test Preliminary Failure Detected Test  2010 Microchip Technology Inc. ...

Page 69

... SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Duplicate frequency derived from HFINTOSC. Note 1:  2010 Microchip Technology Inc. R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Section 5 ...

Page 70

... HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS41413B-page 70 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Conditional Preliminary R-0/0 R-0/q LFIOFR HFIOFS bit 0  2010 Microchip Technology Inc. ...

Page 71

... CONFIG1 7:0 CP MCLRE — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Legend: PIC12F1822/16F1823 only. Note 1:  2010 Microchip Technology Inc. R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

Page 72

... PIC12F/LF1822/PIC16F/LF1823 NOTES: DS41413B-page 72 Preliminary  2010 Microchip Technology Inc. ...

Page 73

... The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values.  2010 Microchip Technology Inc. 6.3 Conflicts with the CLKR pin There are two cases when the reference clock output signal cannot be output to the CLKR pin, if: • ...

Page 74

... DS41413B-page 74 R/W-1/1 R/W-0/0 R/W-0/0 CLKRDC<1:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (3) (1) (2) /4. See Section 6.3 “Conflicts with the CLKR pin” Preliminary R/W-0/0 R/W-0/0 CLKRDIV<2:0> bit 0 for details.  2010 Microchip Technology Inc. ...

Page 75

... Bit -/6 13:8 — — CONFIG1 7:0 CP MCLRE — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. Legend:  2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC0 CLKRDIV2 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 ...

Page 76

... PIC12F/LF1822/PIC16F/LF1823 NOTES: DS41413B-page 76 Preliminary  2010 Microchip Technology Inc. ...

Page 77

... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable  2010 Microchip Technology Inc. PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41413B-page 77 ...

Page 78

... V for a DD BOR , the device BORDC for more information. Device Device Operation upon Operation upon wake- up from release of POR Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD  2010 Microchip Technology Inc. ...

Page 79

... BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive  2010 Microchip Technology Inc. T BORRDY BOR Protection Active (1) T PWRT < T PWRT ...

Page 80

... Upon bringing MCLR high, the device will begin execution immediately (see is useful for testing purposes or to synchronize more than one device operating in parallel. Section 10.0 Table 7-4 Preliminary Timer configuration. See for more information. Figure 7-4). This  2010 Microchip Technology Inc. ...

Page 81

... PIC12F/LF1822/PIC16F/LF1823 FIGURE 7-4: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC  2010 Microchip Technology Inc. T PWRT T MCLR T OST Preliminary DS41413B-page 81 ...

Page 82

... Program Counter 0000h ---1 1000 0000h ---u uuuu 0000h ---1 0uuu 0000h ---0 uuuu ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition STATUS PCON Register Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu  2010 Microchip Technology Inc. ...

Page 83

... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)  2010 Microchip Technology Inc. 7-2. U-0 R/W/HC-1/q R/W/HC-1/q — ...

Page 84

... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. Note 1: DS41413B-page 84 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — RMCLR RI — Preliminary Register Bit 1 Bit 0 on Page — BORRDY 79 POR BOR 103  2010 Microchip Technology Inc. ...

Page 85

... A block diagram of the interrupt logic is shown in Figure 8-1 and Figure 8-2. FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 8-2)  2010 Microchip Technology Inc. Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE PEIE GIE Preliminary Interrupt to CPU DS41413B-page 85 ...

Page 86

... PERIPHERAL INTERRUPT LOGIC TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR1IF TMR1IE TMR2IF TMR2IE EEIF EEIE OSFIF OSFIE C1IF C1IE (1) C2IF C2IE (1) BCLIF BCLIE PIC16F/LF1823 only. Note 1: DS41413B-page 86 Preliminary  2010 Microchip Technology Inc. To Interrupt Logic (Figure 8-1) ...

Page 87

... All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.  2010 Microchip Technology Inc. 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...

Page 88

... Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP Preliminary 0005h Inst(0004h) 0005h Inst(0004h) 0004h 0005h NOP Inst(0004h) Inst(0005h) 0004h 0005h NOP NOP Inst(0004h)  2010 Microchip Technology Inc. ...

Page 89

... Asynchronous interrupt latency = 3-5 T Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT not available in all Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in 5: INTF is enabled to be set any time during the Q4-Q1 cycles.  2010 Microchip Technology Inc ...

Page 90

... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. DS41413B-page 90 Preliminary  2010 Microchip Technology Inc. ...

Page 91

... None of the interrupt-on-change pins have changed state The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCAF register Note 1: have been cleared by software.  2010 Microchip Technology Inc. Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...

Page 92

... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 R/W-0/0 TXIE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 TMR2IE TMR1IE bit 0  2010 Microchip Technology Inc. ...

Page 93

... BCLIE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 2-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 ...

Page 94

... R-0/0 R/W-0/0 R/W-0/0 TXIF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary  2010 Microchip Technology Inc. should ensure the R/W-0/0 R/W-0/0 TMR2IF TMR1IF bit 0 ...

Page 95

... Interrupt is not pending bit 2-0 Unimplemented: Read as ‘0’ PIC16F/LF1823 only. Note 1:  2010 Microchip Technology Inc. Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. ...

Page 96

... PS2 RCIE TXIE SSP1IE CCP1IE C1IE EEIE BCL1IE — RCIF TXIF SSP1IF CCP1IF C1IF EEIF BCL1IF — Preliminary Register Bit 1 Bit 0 on Page INTF IOCIF 91 PS1 PS0 175 TMR2IE TMR1IE 92 — — 93 TMR2IF TMR1IF 94 — — 95  2010 Microchip Technology Inc. ...

Page 97

... Converter (DAC) Module” Section 14.0 “Fixed for more information on Voltage Reference (FVR)” these modules.  2010 Microchip Technology Inc. 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2 ...

Page 98

... SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP OST (3) T Interrupt Latency (4) Processor in Sleep Inst( Dummy Cycle Inst( Preliminary 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h)  2010 Microchip Technology Inc. ...

Page 99

... C2IF STATUS — — WDTCON — — WDTPS4 — = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode. Legend: PIC16F/LF1823 only. Note 1:  2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 INTE IOCIE TMR0IF IOCAF4 IOCAF3 IOCAF2 IOCAN4 IOCAN3 ...

Page 100

... PIC12F/LF1822/PIC16F/LF1823 NOTES: DS41413B-page 100 Preliminary  2010 Microchip Technology Inc. ...

Page 101

... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep  2010 Microchip Technology Inc. 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41413B-page 101 ...

Page 102

... Active event. See Section 3.0 “Memory Organization” Active The STATUS register information. Disabled Active Disabled Disabled Preliminary Section 5.0 “Oscillator for more and (Register 3-1) for more WDT Cleared Cleared until the end of OST Unaffected  2010 Microchip Technology Inc. ...

Page 103

... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored.  2010 Microchip Technology Inc. R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets 17 ...

Page 104

... PIC12F/LF1822/PIC16F/LF1823 NOTES: DS41413B-page 104 Preliminary  2010 Microchip Technology Inc. ...

Page 105

... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory.  2010 Microchip Technology Inc. 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...

Page 106

... CPU is able to read and write data to the data EEPROM recommended to code-protect the pro- gram memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. Preliminary  2010 Microchip Technology Inc. (Register 5-1) ...

Page 107

... FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) INSTR( BSF EECON1,RD executed here executed here RD bit EEDATH EEDATL Register EERHLT  2010 Microchip Technology Inc. EEADRH,EEADRL PC+3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( INSTR( ...

Page 108

... NOPs. This prevents the user from executing a two-cycle instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit. Number of Boundary 16 words, = 0000 Preliminary instruction on the next  2010 Microchip Technology Inc. ...

Page 109

... Initiate read NOP ; Executed NOP ; Ignored BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location  2010 Microchip Technology Inc. (Figure 11-1) (Figure 11-1) Preliminary DS41413B-page 109 ...

Page 110

... However, the entire write latch block will be written to program memory. An example of the complete write sequence for eight words is shown in Example loaded into the EEADRH:EEADRL register pair; the eight words of data are loaded using indirect addressing. Preliminary  2010 Microchip Technology Inc. 11-5. The initial address is ...

Page 111

... EEADRL<3:0> = 0000 EEADRL<3:0> = 0001 Buffer Register  2010 Microchip Technology Inc. continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...

Page 112

... Write AAh ; Set WR bit to begin erase ; Any instructions here are ignored as processor ; halts to begin erase sequence ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary  2010 Microchip Technology Inc. ...

Page 113

... EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE  2010 Microchip Technology Inc. ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...

Page 114

... Table When read access is initiated on an address outside the parameters listed in register pair is cleared. Function Read Access User IDs Yes Yes Yes Figure 11-1) Figure 11-1) Preliminary 11-2. Table 11-2, the EEDATH:EEDATL Write Access Yes No No  2010 Microchip Technology Inc. ...

Page 115

... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue  2010 Microchip Technology Inc. Preliminary DS41413B-page 115 ...

Page 116

... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 EEADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0  2010 Microchip Technology Inc. ...

Page 117

... RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read.  2010 Microchip Technology Inc. R/W/HC-0/0 R/W-x/q R/W-0/0 FREE ...

Page 118

... WREN EEADRL<7:0> EEADRH<6:0> EEDATL<7:0> EEDATH<5:0> INTE IOCIE TMR0IF EEIE BCL1IE — EEIF BCL1IF — Preliminary W-0/0 W-0/0 bit 0 Register Bit 1 Bit 0 on Page WR RD 117 118* 116 116 116 116 INTF IOCIF 91 — — 93 — — 95  2010 Microchip Technology Inc. ...

Page 119

... Ports with analog functions also have an ANSELx register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1.  2010 Microchip Technology Inc. FIGURE 12-1: Write LATx Write PORTx Data Bus Read PORTx To peripherals ● ...

Page 120

... SDO • SS (Slave Select) • T1G • P1B • CCP1/P1A These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. DS41413B-page 120 Preliminary  2010 Microchip Technology Inc. ...

Page 121

... CCP1/P1A function is on RA2 1 = CCP1/P1A function is on RA5 For 14 Pin Devices (PIC16F/LF1823): CCP1/P1A function is always on RC5 PIC12F/LF1822 only. Note 1:  2010 Microchip Technology Inc. U-0 R/W-0/0 R/W-0/0 T1GSEL TXCKSEL — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

Page 122

... PORTA ; CLRF PORTA ;Init PORTA BANKSEL LATA ;Data Latch CLRF LATA ; BANKSEL ANSELA ; CLRF ANSELA ;digital I/O BANKSEL TRISA ; MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA ;and set RA<2:0> as ;outputs DS41413B-page 122 12-2) reads the Preliminary  2010 Microchip Technology Inc. ...

Page 123

... ICDCLK 3. SCL (PIC12F/LF1822 only) 4. RX/DT (EUSART) 5. SCK (PIC12F/LF1822 only) RA2 1. SRQ 2. C1OUT (Comparator) 3. SDA (PIC12F/LF1822 only) 4. CCP1/P1A (PIC12F/LF1822 only)  2010 Microchip Technology Inc. RA3 No output priorities. Input only pin. RA4 1. OSC2 2. CLKOUT 3. T1OSO (Timer1 Oscillator) 4. CLKR 5. TX/CK (PIC12F/LF1822 only) 6. SDO 7 ...

Page 124

... Value at POR and BOR/Value at all other Resets (1) R/W-1/1 R-1/1 R/W-1/1 TRISA4 TRISA3 TRISA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/x R/W-x/x RA1 RA0 bit 0 R/W-1/1 R/W-1/1 TRISA1 TRISA0 bit 0  2010 Microchip Technology Inc. ...

Page 125

... Digital I/O. Pin is assigned to port or digital special function Analog input. Pin is assigned as analog input When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin.  2010 Microchip Technology Inc. R/W-x/u U-0 R/W-x/u LATA4 — ...

Page 126

... Bit -/7 Bit -/6 13:8 — — CONFIG1 7:0 CP MCLRE — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. Legend: PIC12F1822/16F1823 only. Note 1: DS41413B-page 126 R/W-1/1 R/W-1/1 R/W-1/1 WPUA4 WPUA3 WPUA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

Page 127

... BANKSEL TRISB ; MOVLW B’00110000’;Set RC<5:4> as inputs ;and RC<3:0> as outputs MOVWF TRISC ;  2010 Microchip Technology Inc. 12.3.2 PORTC FUNCTIONS AND OUTPUT PRIORITIES Each PORTC pin is multiplexed with other functions. The pins, their combined functions and their output priorities is TRISC are briefly described here ...

Page 128

... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATC4 LATC3 LATC2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RC1 RC0 bit 0 R/W-1/1 R/W-1/1 TRISC1 TRISC0 bit 0 R/W-x/u R/W-x/u LATC1 LATC0 bit 0  2010 Microchip Technology Inc. ...

Page 129

... WPUC — — unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Legend: PIC16F/LF1823 only. Note 1:  2010 Microchip Technology Inc. U-0 R/W-1/1 R/W-1/1 — ANSC3 ANSC2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) ...

Page 130

... Sleep mode, if the IOCIE bit is set edge is detected while in Sleep mode, the IOCAF register will be updated prior to the first instruction executed out of Sleep. IOCAFx From all other IOCAFx individual pin detectors Q2 Clock Cycle Preliminary  2010 Microchip Technology Inc. IOCIE IOC Interrupt to CPU Core ...

Page 131

... An enabled change was detected on the associated pin. Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was detected on RAx change was detected, or the user cleared the detected change.  2010 Microchip Technology Inc. R/W-0/0 R/W-0/0 R/W-0/0 ...

Page 132

... IOCAF2 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAP5 IOCAP4 IOCAP3 IOCAP2 TRISA5 TRISA4 TRISA3 TRISA2 Preliminary Register Bit 1 Bit 0 on Page ANSA1 ANSA0 125 INTF IOCIF 91 IOCAF1 IOCAF0 131 IOCAN1 IOCAN0 131 IOCAP1 IOCAP0 131 TRISA1 TRISA0 124  2010 Microchip Technology Inc. ...

Page 133

... PIC12F/LF1822/PIC16F/LF1823 NOTES:  2010 Microchip Technology Inc. Preliminary DS41413B-page 133 ...

Page 134

... Section 30.0 “Electrical Specifications” minimum delay requirement (To Comparators, DAC, CPS 1.024V Fixed _ Reference Preliminary for additional information. Section 17.0 “Digital-to- Module”, Section 19.0 and Section 27.0 “Capacitive for additional information. for the FVR BUFFER1 (To ADC Module) FVR BUFFER2  2010 Microchip Technology Inc. ...

Page 135

... ADC Fixed Voltage Reference Peripheral output is off 01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V ADC Fixed Voltage Reference Peripheral output is 2x (2.048V ADC Fixed Voltage Reference Peripheral output is 4x (4.096V) FVRRDY is always ‘1’ on PIC12F1822/16F1823 only. Note 1: Fixed Voltage Reference output cannot exceed V 2: ...

Page 136

... PIC12F/LF1822/PIC16F/LF1823 NOTES: DS41413B-page 136 Preliminary  2010 Microchip Technology Inc. ...

Page 137

... The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation.  2010 Microchip Technology Inc. FIGURE 15-1: 15.2 Minimum Operating V Minimum Sensing Temperature ...

Page 138

... PIC12F/LF1822/PIC16F/LF1823 NOTES: DS41413B-page 138 Preliminary  2010 Microchip Technology Inc. ...

Page 139

... Temp Indicator DAC FVR Buffer1 CHS<4:0> Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2: Not available on PIC12F/LF1822.  2010 Microchip Technology Inc. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) allows ...

Page 140

... Unless using the F Note: system clock frequency will change the ADC adversely affect the ADC result. Section 16.2 Preliminary peri- AD Figure 16-2. specifica- AD for Table 16-1 gives examples of appro- , any changes in the RC clock frequency, which may  2010 Microchip Technology Inc. ...

Page 141

... Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit  2010 Microchip Technology Inc DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 20 MHz 16 MHz (2) 100 ns (2) 125 ns (2) (2) (2) (2) 200 ns 250 ns (2) (2) 0.5  ...

Page 142

... ADCON1 register controls the output format. Figure 16-3 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0  2010 Microchip Technology Inc. ...

Page 143

... A device Reset forces all registers to their Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated.  2010 Microchip Technology Inc. 16.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...

Page 144

... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space  2010 Microchip Technology Inc. ...

Page 145

... Section 17.0 “Digital-to-Analog Converter (DAC) Module” See 3: Section 14.0 “Fixed Voltage Reference (FVR)” See 4: Section 15.0 “Temperature Indicator Module”  2010 Microchip Technology Inc. R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

Page 146

... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets DD (1) + REF + pin as the source of the positive reference, be aware that a REF Section 30.0 “Electrical Specifications” Preliminary R/W-0/0 R/W-0/0 ADPREF<1:0> bit 0 (1) for details.  2010 Microchip Technology Inc. ...

Page 147

... Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use.  2010 Microchip Technology Inc. R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

Page 148

... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES<9:8> bit 0 R/W-x/u R/W-x/u bit 0  2010 Microchip Technology Inc. ...

Page 149

... The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.  2010 Microchip Technology Inc. source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...

Page 150

... V - REF DS41413B-page 150 V DD Sampling Switch  0.  Rss R IC LEAKAGE (1) I  0. Full-Scale Range 0.5 LSB Zero-Scale Full-Scale Transition V REF Transition Preliminary HOLD REF Sampling Switch (k) Analog Input Voltage 1.5 LSB +  2010 Microchip Technology Inc. ...

Page 151

... TRISC — — — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Legend: * Page provides register information. PIC16F/LF1823 only. Note 1:  2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 CHS3 CHS2 CHS1 CHS0 ADCS1 ADCS0 — ...

Page 152

... PIC12F/LF1822/PIC16F/LF1823 NOTES: DS41413B-page 152 Preliminary  2010 Microchip Technology Inc. ...

Page 153

... The value of the individual resistors within the ladder can be found in Section 30.0 Specifications”.  2010 Microchip Technology Inc. 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. The DAC output voltage is determined by the following equations:  ...

Page 154

... VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41413B-page 154 Digital-to-Analog Converter (DAC) V SOURCE + Steps SOURCE - + DACOUT – Preliminary DACR<4:0> 5 DAC (To Comparator, CPS and ADC Modules) DACOUT DACOE Buffered DAC Output  2010 Microchip Technology Inc. ...

Page 155

... DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared.  2010 Microchip Technology Inc. This is also the method used to output the voltage level from the FVR to an output pin. See “Operation During Sleep” ...

Page 156

... Bit 2 TSEN TSRNG CDAFVR1 CDAFVR0 DACOE — DACPSS1 DACPSS0 — DACR4 DACR3 DACR2 Preliminary U-0 U-0 — — bit 0 R/W-0/0 R/W-0/0 bit 0 Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 135 — — 156 DACR1 DACR0 156  2010 Microchip Technology Inc. ...

Page 157

... Note: from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured.  2010 Microchip Technology Inc. 18.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs. Both of the SR Latch outputs may be directly output to an I/O pin at the same time ...

Page 158

... SYNCC2OUT (4) SRRC2E (3) SYNCC1OUT SRRC1E and simultaneously Note 1: Pulse generator causes a 1 Q-state pulse width. 2: Name denotes the connection point at the comparator output. 3: PIC16F/LF1823 only. 4: DS41413B-page 158 SRLEN SRQEN (1) Latch R Q SRLEN SRNQEN Preliminary  2010 Microchip Technology Inc. SRQ SRNQ ...

Page 159

... Pulse set input for 1 Q-clock period effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse reset input for 1 Q-clock period effect on reset input. Set only, always reads back ‘0’. Note 1:  2010 Microchip Technology Inc MHz MHz OSC OSC 39.0 kHz 31 ...

Page 160

... C1 Comparator output has no effect on the reset input of the SR Latch PIC16F/LF1823 only. Note 1: DS41413B-page 160 R/W-0/0 R/W-0/0 R/W-0/0 (1) SRSC1E SRRPE SRRCKE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) (1) Preliminary R/W-0/0 R/W-0/0 (1) SRRC2E SRRC1E bit 0  2010 Microchip Technology Inc. ...

Page 161

... SRLEN SRCLK2 SRCON1 SRSPE SRSCKE TRISA — — — = unimplemented, read as ‘0’. Shaded cells are unused by the SR Latch module. Legend: PIC16F/LF1823 only. Note 1:  2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 — ANSA2 SRCLK1 SRCLK0 SRQEN SRNQEN ...

Page 162

... PIC12F/LF1822/PIC16F/LF1823 NOTES: DS41413B-page 162 Preliminary  2010 Microchip Technology Inc. ...

Page 163

... When the analog voltage at V less than the analog voltage the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN  2010 Microchip Technology Inc. FIGURE 19- ...

Page 164

... Output of comparator can be frozen during debugging. 3: DS41413B-page 164 (1) Interrupt Interrupt C1POL D ( (from Timer1) T1CLK Preliminary C1INTP det Set C1IF C1INTN det C1OUT To Data Bus Q MC1OUT To ECCP PWM Logic C1SYNC C1OE TRIS bit C1OUT Timer1 or SR Latch SYNCC1OUT  2010 Microchip Technology Inc. ...

Page 165

... FVR Buffer2 3 CxON PCH<1:0> When CxON = 0, the Comparator will produce a ‘0’ at the output. Note 1: When CxON = 0, all multiplexer inputs are disconnected. 2: Output of comparator can be frozen during debugging. 3:  2010 Microchip Technology Inc. (1) Interrupt Interrupt C POL CxHYS D (from Timer1) T1CLK ...

Page 166

... CxSP control bit. The default state for this bit is ‘1’ which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propaga- tion delay by clearing the CxSP bit to ‘0’. Preliminary  2010 Microchip Technology Inc. CxOUT ...

Page 167

... Timer1 Block Diagram (Figure 21-1) information.  2010 Microchip Technology Inc. 19.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a Falling edge detector are present. When either edge detector is triggered and its associ- ...

Page 168

... Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. Preliminary  2010 Microchip Technology Inc. and V . The DD SS and V . ...

Page 169

... Legend Input Capacitance PIN I = Leakage Current at the pin due to various junctions LEAKAGE R = Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See Section 30.0 “Electrical Specifications”  2010 Microchip Technology Inc  0. (1) LEAKAGE  0. Vss Preliminary To Comparator DS41413B-page 169 ...

Page 170

... Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous. DS41413B-page 170 R/W-0/0 U-0 R/W-1/1 CxPOL CxSP — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 CxHYS CxSYNC bit 0  2010 Microchip Technology Inc. ...

Page 171

... Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit PIC16F/LF1823 only. Note 1:  2010 Microchip Technology Inc. R/W-0/0 U-0 CxPCH<1:0> — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

Page 172

... Preliminary Register Bit 1 Bit 0 on Page ANSA1 ANSA0 125 C1HYS C1SYNC 170 (1) C1NCH1 C1NCH0 171 C2HYS C2SYNC 170 C2NCH1 C2NCH0 171 (1) MC2OUT MC1OUT 171 INTF IOCIF 91 — — 92 — — 95 TRISA1 TRISA0 124 TRISC1 TRISC0 128  2010 Microchip Technology Inc. ...

Page 173

... From CPSCLK 1 TMR0SE TMR0CS T0XCS  2010 Microchip Technology Inc. 20.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION register to ‘ ...

Page 174

... Section 30.0 “Electrical Specifications”. 20.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41413B-page 174 Preliminary  2010 Microchip Technology Inc. ...

Page 175

... Timer0 Module Register TRISA — — Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information.  2010 Microchip Technology Inc. R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

Page 176

... PIC12F/LF1822/PIC16F/LF1823 NOTES: DS41413B-page 176 Preliminary  2010 Microchip Technology Inc. ...

Page 177

... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.  2010 Microchip Technology Inc. • Gate Toggle Mode • Gate Single-pulse Mode • Gate Value Status • Gate Event Interrupt Figure 21 block diagram of the Timer1 module ...

Page 178

... T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. T1OSCEN System Clock (F ) OSC x Instruction Clock (F OSC x Capacitive Sensing Oscillator x External Clocking on T1CKI Pin 0 Osc.Circuit On T1OSI/T1OSO Pins 1 Preliminary internal clock source is selected, the system clock or they can run Clock Source /4)  2010 Microchip Technology Inc. ...

Page 179

... A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair.  2010 Microchip Technology Inc. 21.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry ...

Page 180

... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). Preliminary Figure 21-6 for  2010 Microchip Technology Inc. ...

Page 181

... TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2010 Microchip Technology Inc. 21.9 ECCP/CCP Capture/Compare Time Base The CCP1 module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...

Page 182

... PIC12F/LF1822/PIC16F/LF1823 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41413B-page 182 Preliminary  2010 Microchip Technology Inc ...

Page 183

... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF  2010 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41413B-page 183 ...

Page 184

... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41413B-page 184 Set by hardware on falling edge of T1GVAL Preliminary  2010 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Cleared by software ...

Page 185

... This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop  2010 Microchip Technology Inc. R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

Page 186

... Comparator 1 optionally synchronized output (SYNCC1OUT Comparator 2 optionally synchronized output (SYNCC2OUT) DS41413B-page 186 R/W-0/u R/W/HC-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware Preliminary R/W-0/u R/W-0/u T1GSS<1:0> bit 0  2010 Microchip Technology Inc. ...

Page 187

... TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T1CON TMR1GE T1GPOL T1GCON Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. PIC16F/LF1823 only. Note 1:  2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 — ANSA2 DC1B1 ...

Page 188

... Figure 22-1 for a block diagram of Timer2. FIGURE 22-1: TIMER2 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 T2CKPS<1:0> DS41413B-page 188 TMR2 Output Reset TMR2 Postscaler Comparator 1 PR2 T2OUTPS<3:0> Preliminary Sets Flag bit TMR2IF  2010 Microchip Technology Inc. ...

Page 189

... TMR2IE of the PIE1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0>, of the T2CON register.  2010 Microchip Technology Inc. 22.3 Timer2 Output The unscaled output of TMR2 is available primarily to the CCP1 module, where it is used as a time base for operations in PWM mode ...

Page 190

... T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler Prescaler is 64 DS41413B-page 190 R/W-0/0 R/W-0/0 R/W-0/0 TMR2ON U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 T2CKPS<1:0> bit 0  2010 Microchip Technology Inc. ...

Page 191

... T2CON — TMR2 Holding Register for the 8-bit TMR2 Register Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information.  2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE ...

Page 192

... PIC12F/LF1822/PIC16F/LF1823 NOTES: DS41413B-page 192 Preliminary  2010 Microchip Technology Inc. ...

Page 193

... MDCLPOL * No Channel * Selected 1111  2010 Microchip Technology Inc. Using this method, the DSM can generate the following types of Key Modulation schemes: • Frequency-Shift Keying (FSK) • Phase-Shift Keying (PSK) • On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: • ...

Page 194

... MDCHSYNC bit in the MDCARH register. Synchroniza- tion for the carrier low signal can be enabled by setting the MDCLSYNC bit in the MDCARL register. Figure 23-1 through Figure 23-5 of using various synchronization methods. Preliminary  2010 Microchip Technology Inc. show timing diagrams ...

Page 195

... CARH Active Carrier State FIGURE 23-3: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 CARH Active Carrier State  2010 Microchip Technology Inc. CARL CARH CARH CARL both Preliminary CARL both CARL DS41413B-page 195 ...

Page 196

... Active Carrier CARH State FIGURE 23-5: FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier CARH State DS41413B-page 196 CARL CARH CARL CARH Preliminary  2010 Microchip Technology Inc. CARL CARL ...

Page 197

... DSM can still operate during Sleep, if the Carrier and Modulator input sources are also still operable during Sleep.  2010 Microchip Technology Inc. 23.12 Effects of a Reset Upon any device Reset, the Data Signal Modulator module is disabled. The user’s firmware is responsible for initializing the module before enabling the output ...

Page 198

... MDBIT must be selected as the modulation source in the MDSRC register for this operation. 2: DS41413B-page 198 R/W-0/0 R-0/0 U-0 MDOPOL MDOUT — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary U-0 R/W-0/0 — MDBIT bit 0 (2)  2010 Microchip Technology Inc. ...

Page 199

... CCP1 output (PWM Output mode only) 0001 = MDMIN port pin 0000 = MDBIT bit of MDCON register is modulation source Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. Note 1:  2010 Microchip Technology Inc. U-0 R/W-x/u R/W-x/u — ...

Page 200

... Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. Note 1: DS41413B-page 200 U-0 R/W-x/u R/W-x/u — MDCH<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary  2010 Microchip Technology Inc. R/W-x/u R/W-x/u bit 0 (1) ...

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