PIC12F1840T-I/SN Microchip Technology, PIC12F1840T-I/SN Datasheet
PIC12F1840T-I/SN
Specifications of PIC12F1840T-I/SN
Available stocks
Related parts for PIC12F1840T-I/SN
PIC12F1840T-I/SN Summary of contents
Page 1
... Microchip Technology Inc. PIC12(L)F1840 8-Pin Flash Microcontrollers with nanoWatt XLP Technology Preliminary Data Sheet DS41441B ...
Page 2
... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... Enhanced Low-Voltage Programming (LVP) • Operating Voltage Range: - 2.3V-5.5V (PIC12F1840) - 1.8V-3.6V (PIC12LF1840) • Programmable Code Protection • Power-Saving Sleep mode 2011 Microchip Technology Inc. PIC12(L)F1840 Low-Power Features: • Standby Current (PIC12LF1840 1.8V, typical • Operating Current (PIC12LF1840 MHz, 1.8V, typical • ...
Page 4
... Multiple Set/Reset input options - Emulates 555 Timer applications PIC12(L)F1840 Family Types Program Data Memory Memory PIC12LF1840 4K 256 PIC12F1840 4K 256 One pin is input only. Note 1: DS41441B-page 4 256 2/1 256 2/1 Preliminary 1 1 — 1 Yes 1 1 — 1 Yes 2011 Microchip Technology Inc. ...
Page 5
FIGURE 1: 8-PIN DIAGRAM FOR PIC12(L)F1840 PDIP, SOIC, DFN (1) (1) (1) (1) RX /DT /CCP1 /P1A /SRNQ/T1CKI/T1OSI/OSC1/CLKIN/RA5 (1) (1) (1) (1) (1) MDCIN2/T1G /P1B /TX /CK /SDO /CLKR/C1IN1-/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 Pin function is selectable via the APFCON register. Note 1: TABLE ...
Page 6
... Packaging Information.............................................................................................................................................................. 361 Appendix A: Revision History............................................................................................................................................................. 371 Appendix B: Device Differences......................................................................................................................................................... 371 Index .................................................................................................................................................................................................. 371 The Microchip Web Site ..................................................................................................................................................................... 379 Customer Change Notification Service .............................................................................................................................................. 379 Customer Support .............................................................................................................................................................................. 379 Reader Response .............................................................................................................................................................................. 380 Product Identification System............................................................................................................................................................. 381 DS41441B-page 6 ) ................................................................................................................................ 303 ™ Preliminary 2011 Microchip Technology Inc. ...
Page 7
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com 2011 Microchip Technology Inc. PIC12(L)F1840 to receive the most current information on all of our products. Preliminary DS41441B-page 7 ...
Page 8
... PIC12(L)F1840 NOTES: DS41441B-page 8 Preliminary 2011 Microchip Technology Inc. ...
Page 9
... Digital Signal Modulator (DSM) EUSART Fixed Voltage Reference (FVR) SR Latch Capture/Compare/PWM Modules ECCP1 Comparators Master Synchronous Serial Ports MSSP Timers Timer0 Timer1 Timer2 2011 Microchip Technology Inc. shows a Table 1-2 ● ● ● ● ● ● ● ● ● C1 ● ...
Page 10
... See applicable chapters for more information on peripherals. Note 1: See Table 1-1 for peripherals available on specific devices. 2: DS41441B-page 10 Program Flash Memory RAM CPU (Figure 2-1) ADC Timer1 DAC Comparators 10-Bit Modulator FVR EUSART CapSense Preliminary EEPROM PORTA 2011 Microchip Technology Inc. ...
Page 11
... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Pin functions can be assigned to one of two pin locations via software. See APFCON register Note 1: 2011 Microchip Technology Inc. PIC12(L)F1840 Input Output Type Type TTL CMOS General purpose I/O ...
Page 12
... CMOS USART synchronous data. ST — USART asynchronous input. Power — Positive supply. Power — Ground reference. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels (Register 12-1). 2011 Microchip Technology Inc. ...
Page 13
... Section 3.5 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 “Instruction Set Summary” details. 2011 Microchip Technology Inc. PIC12(L)F1840 for more Preliminary DS41441B-page 13 ...
Page 14
... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W Reg Timer Brown-out Reset Preliminary RAM Addr 12 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX 2011 Microchip Technology Inc. ...
Page 15
... Section 11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC12(L)F1840 2011 Microchip Technology Inc. The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3 ...
Page 16
... If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 7FFFh Preliminary Example 3-1. RETLW INSTRUCTION ;Add Index ;program counter to ;select data ;Index0 data ;Index1 data 2011 Microchip Technology Inc. ...
Page 17
... File Select Registers (FSR). See Section 3.5 for more information. Addressing” 2011 Microchip Technology Inc. PIC12(L)F1840 3.2.1 CORE REGISTERS The core registers contain the registers that directly affect the basic operation of the PIC12(L)F1840. These registers are listed below: • ...
Page 18
... Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. R-1/q R-1/q R/W-0 Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) Preliminary Section 29.0 Summary”). R/W-0/u R/W-0/u (1) ( bit 0 2011 Microchip Technology Inc. ...
Page 19
... General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) 7Fh 2011 Microchip Technology Inc. 3.2.5 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: Device PIC12(L)F1840 Section 3.5.2 ...
Page 20
TABLE 3-3: PIC12(L)F1840 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H ...
Page 21
TABLE 3-4: PIC12(L)F1840 MEMORY MAP, BANKS 8-23 BANK 8 BANK 9 INDF0 INDF0 x00h x80h x00h INDF1 INDF1 x01h x81h x01h PCL PCL x02h x82h x02h STATUS STATUS x03h x83h x03h FSR0L FSR0L x04h x84h x04h FSR0H FSR0H x05h x85h ...
Page 22
TABLE 3-5: PIC12(L)F1840 MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H ...
Page 23
... FECh FEDh STKPTR FEEh TOSL FEFh TOSH = Unimplemented data memory locations, Legend: read as ‘0’. 2011 Microchip Technology Inc. PIC12(L)F1840 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device PIC12(L)F1840 Preliminary Bank(s) Page No ...
Page 24
... TMR1ON 0000 00-0 uuuu uu-u T1GSS<1:0> 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111 T2CKPS<1:0> -000 0000 -000 0000 — — CPSOUT T0XCS 00-- 0000 00-- 0000 CPSCH<1:0> ---- --00 ---- --00 2011 Microchip Technology Inc. ...
Page 25
... ADFM 09Fh — Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC12F1840 only. 2011 Microchip Technology Inc. PIC12(L)F1840 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
Page 26
... ADFVR<1:0> 0q00 0000 0q00 0000 — — 000- 00-- 000- 00-- ---0 0000 ---0 0000 SRPS SRPR 0000 0000 0000 0000 Reserved SRRC1E 0000 0000 0000 0000 — — P1BSEL CCP1SEL 000- 0000 000- 0000 — — — — 2011 Microchip Technology Inc. ...
Page 27
... BAUDCON ABDOVF RCIDL x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC12F1840 only. 2011 Microchip Technology Inc. PIC12(L)F1840 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
Page 28
... RSEN SEN 0000 0000 0000 0000 AHEN DHEN 0000 0000 0000 0000 — — — — — — — — — — — — — — — — 2011 Microchip Technology Inc. ...
Page 29
... Unimplemented 29Fh — Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC12F1840 only. 2011 Microchip Technology Inc. PIC12(L)F1840 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
Page 30
... Microchip Technology Inc. ...
Page 31
... MDCARH MDCHODIS MDCHPOL MDCHSYNC x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC12F1840 only. 2011 Microchip Technology Inc. PIC12(L)F1840 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
Page 32
... INTF IOCIF 0000 000x 0000 000u — — 2011 Microchip Technology Inc. ...
Page 33
... Top-of-Stack High byte TOSH x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC12F1840 only. 2011 Microchip Technology Inc. PIC12(L)F1840 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
Page 34
... If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will 0 be loaded with the address BRW If using BRA, the entire PC will be loaded with the signed value of the operand of the BRA instruction. 0 BRA Preliminary 2011 Microchip Technology Inc. ...
Page 35
... RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2011 Microchip Technology Inc. PIC12(L)F1840 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...
Page 36
... Program Counter and pop the stack. 0x09 0x08 0x07 STKPTR = 0x06 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address Preliminary 2011 Microchip Technology Inc. ...
Page 37
... The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory 2011 Microchip Technology Inc. PIC12(L)F1840 0x0F Return Address 0x0E Return Address ...
Page 38
... Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41441B-page 38 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Preliminary 2011 Microchip Technology Inc. ...
Page 39
... FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2 2011 Microchip Technology Inc. PIC12(L)F1840 Indirect Addressing 0 7 FSRxH Bank Select 11111 Bank 31 Preliminary ...
Page 40
... FIGURE 3-11: 7 FSRnH 0 1 Location Select 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F 0xF20 Bank 30 0xF6F Preliminary the FSR/INDF interface. All PROGRAM FLASH MEMORY MAP FSRnL 0x8000 0x0000 Program Flash Memory (low 8 bits) 0x7FFF 0xFFFF 2011 Microchip Technology Inc. ...
Page 41
... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word 2 is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2011 Microchip Technology Inc. by device Preliminary PIC12(L)F1840 DS41441B-page 41 ...
Page 42
... R/P-1/1 R/P-1/1 R/P-1/1 WDTE1 WDTE0 FOSC2 U = Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) (3) Pin Function Select bit (1) Preliminary R/P-1/1 R/P-1/1 CPD CP bit 7 R/P-1/1 R/P-1/1 FOSC1 FOSC0 bit 0 2011 Microchip Technology Inc. ...
Page 43
... Enabling Brown-out Reset does not automatically enable Power-up Timer. Note 1: The entire data EEPROM will be erased when the code protection is turned off during an erase. 2: The entire program memory will be erased when the code protection is turned off. 3: 2011 Microchip Technology Inc. PIC12(L)F1840 Preliminary DS41441B-page 43 ...
Page 44
... R/P-1/1 — BORV STVREN R-1 U-1 U-1 — — Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) Preliminary R/P-1/1 U-1 PLLEN — bit 7 R/P-1/1 R/P-1/1 WRT1 WRT0 bit 0 2011 Microchip Technology Inc. ...
Page 45
... See Section 11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16F/LF1847/PIC12F/LF1840 Memory Programming Specification” (DS41439). 2011 Microchip Technology Inc. PIC12(L)F1840 “Write such as Preliminary ...
Page 46
... These bits are used to identify the revision. This location cannot be written. Note 1: DS41441B-page 46 ( DEV6 DEV5 DEV4 REV4 REV3 REV2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Preliminary R R DEV3 DEV2 bit REV1 REV0 bit 0 2011 Microchip Technology Inc. ...
Page 47
... XT, HS modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources. 2011 Microchip Technology Inc. PIC12(L)F1840 The oscillator module can be configured in one of eight clock modes. 1. ECL – External Clock Low Power mode (0 MHz to 0 ...
Page 48
... WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules Preliminary Sleep CPU and T1OSC Peripherals Clock Control FOSC<2:0> SCS<1:0> Clock Source Option for other modules 2011 Microchip Technology Inc. ...
Page 49
... High-power, 4-32 MHz (FOSC = 111) • Medium power, 0.5-4 MHz (FOSC = 110) • Low-power, 0-0.5 MHz (FOSC = 101) 2011 Microchip Technology Inc. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...
Page 50
... Preliminary CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic R (3) ( Sleep F OSC2/CLKOUT R S (1) ) may be required for S varies with the Oscillator mode F P Oscillator Start-up Timer (OST) Section 5.4 Mode”). 4X PLL Specifications in Section 30.0 2011 Microchip Technology Inc. ) ...
Page 51
... MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288) 2011 Microchip Technology Inc. 5.2.1.6 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...
Page 52
... OSCSTAT register indicates when the MFINTOSC is running and can be utilized. Preliminary (Register 5-3). Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information. Internal Oscillator Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information. 2011 Microchip Technology Inc. ...
Page 53
... Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. 2011 Microchip Technology Inc. PIC12(L)F1840 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits 5-3) ...
Page 54
... Clock switching time delays are shown in Start-up delay specifications are located in the oscillator tables of Specifications” Preliminary 2011 Microchip Technology Inc. Figure 5-7). If this is the Table 5-1. Section 30.0 “Electrical ...
Page 55
... IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock 2011 Microchip Technology Inc. Start-up Time 2-cycle Sync 0 2-cycle Sync LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync 0 Preliminary ...
Page 56
... The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. Start-up or Preliminary Section 21.0 for more 2011 Microchip Technology Inc. ...
Page 57
... LFINTOSC Any clock source Timer1 Oscillator PLL inactive PLL active PLL inactive. Note 1: 2011 Microchip Technology Inc. 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Word Inter- nal/External Switchover bit (Two-Speed Start-up mode enabled). • ...
Page 58
... CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator Preliminary 2011 Microchip Technology Inc. ...
Page 59
... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. 2011 Microchip Technology Inc. 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...
Page 60
... Clock Monitor Output (Q) OSCFIF The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in Note: this example have been chosen for clarity. DS41441B-page 60 Oscillator Failure Test Test Preliminary Failure Detected Test 2011 Microchip Technology Inc. ...
Page 61
... SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Duplicate frequency derived from HFINTOSC. Note 1: 2011 Microchip Technology Inc. R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Section 5 ...
Page 62
... HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS41441B-page 62 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Conditional Preliminary R-0/0 R-0/q LFIOFR HFIOFS bit 0 2011 Microchip Technology Inc. ...
Page 63
... CP MCLRE — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Legend: PIC12F1840 only. Note 1: 2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Bit 5 ...
Page 64
... PIC12(L)F1840 NOTES: DS41441B-page 64 Preliminary 2011 Microchip Technology Inc. ...
Page 65
... Upon any device Reset, the reference clock module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. 2011 Microchip Technology Inc. PIC12(L)F1840 6.3 Conflicts with the CLKR pin ...
Page 66
... R/W-0/0 CLKRDC1 CLKRDC0 CLKRDIV2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (3) (1) (2) /4. See Section 6.3 “Conflicts with the CLKR pin” Preliminary R/W-0/0 R/W-0/0 CLKRDIV1 CLKRDIV0 bit 0 for details. 2011 Microchip Technology Inc. ...
Page 67
... Bit -/6 13:8 — — CONFIG1 7:0 CP MCLRE — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. Legend: 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC0 CLKRDIV2 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 ...
Page 68
... PIC12(L)F1840 NOTES: DS41441B-page 68 Preliminary 2011 Microchip Technology Inc. ...
Page 69
... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2011 Microchip Technology Inc. PIC12(L)F1840 PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41441B-page 69 ...
Page 70
... V for a DD BOR , the device BORDC for more information. Device Device Operation upon Operation upon wake- up from release of POR Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD 2011 Microchip Technology Inc. ...
Page 71
... If BOREN <1:0> in Configuration Word BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive 2011 Microchip Technology Inc. PIC12(L)F1840 T BORRDY BOR Protection Active (1) T PWRT < T ...
Page 72
... Upon bringing MCLR high, the device will begin execution immediately (see is useful for testing purposes or to synchronize more than one device operating in parallel. Table 7-4 Preliminary Timer configuration. See for more information. Figure 7-4). This 2011 Microchip Technology Inc. ...
Page 73
... FIGURE 7-4: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2011 Microchip Technology Inc. PIC12(L)F1840 T PWRT T MCLR T OST Preliminary DS41441B-page 73 ...
Page 74
... Program Counter 0000h ---1 1000 0000h ---u uuuu 0000h ---1 0uuu 0000h ---0 uuuu ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition STATUS PCON Register Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu 2011 Microchip Technology Inc. ...
Page 75
... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2011 Microchip Technology Inc. PIC12(L)F1840 7-2. U-0 R/W/HC-1/q R/W/HC-1/q — ...
Page 76
... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. Note 1: DS41441B-page 76 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — RMCLR RI — WDTPS<4:0> Preliminary Register Bit 1 Bit 0 on Page — BORRDY 71 POR BOR SWDTEN 95 2011 Microchip Technology Inc. ...
Page 77
... A block diagram of the interrupt logic is shown in Figure 8-1 and Figure 8-2. FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 8-2) 2011 Microchip Technology Inc. Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE PEIE GIE Preliminary PIC12(L)F1840 Interrupt to CPU DS41441B-page 77 ...
Page 78
... PIC12(L)F1840 FIGURE 8-2: PERIPHERAL INTERRUPT LOGIC TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR1IF TMR1IE TMR2IF TMR2IE EEIF EEIE C1IF C1IE OSFIF OSFIE BCLIF BCLIE DS41441B-page 78 Preliminary 2011 Microchip Technology Inc. To Interrupt Logic (Figure 8-1) ...
Page 79
... All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 2011 Microchip Technology Inc. PIC12(L)F1840 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...
Page 80
... Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP Preliminary 0005h Inst(0004h) 0005h Inst(0004h) 0004h 0005h NOP Inst(0004h) Inst(0005h) 0004h 0005h NOP NOP Inst(0004h) 2011 Microchip Technology Inc. ...
Page 81
... Asynchronous interrupt latency = 3-5 T Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in 5: INTF is enabled to be set any time during the Q4-Q1 cycles. 2011 Microchip Technology Inc ...
Page 82
... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. DS41441B-page 82 Preliminary 2011 Microchip Technology Inc. ...
Page 83
... None of the interrupt-on-change pins have changed state The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCAF register Note 1: have been cleared by software. 2011 Microchip Technology Inc. PIC12(L)F1840 Interrupt flag bits are set when an interrupt Note: ...
Page 84
... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 R/W-0/0 TXIE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 TMR2IE TMR1IE bit 0 2011 Microchip Technology Inc. ...
Page 85
... BCL1IE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 2-0 Unimplemented: Read as ‘0’ 2011 Microchip Technology Inc. PIC12(L)F1840 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. ...
Page 86
... R-0/0 R/W-0/0 R/W-0/0 TXIF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. should ensure the R/W-0/0 R/W-0/0 TMR2IF TMR1IF bit 0 ...
Page 87
... BCL1IF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2-0 Unimplemented: Read as ‘0’ 2011 Microchip Technology Inc. PIC12(L)F1840 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 88
... PS2 RCIE TXIE SSP1IE CCP1IE C1IE EEIE BCL1IE — RCIF TXIF SSP1IF CCP1IF C1IF EEIF BCL1IF — Preliminary Register Bit 1 Bit 0 on Page INTF IOCIF 83 PS1 PS0 161 TMR2IE TMR1IE 84 — — 85 TMR2IF TMR1IF 86 — — 87 2011 Microchip Technology Inc. ...
Page 89
... Converter (DAC) Module” Section 14.0 “Fixed for more information on Voltage Reference (FVR)” these modules. 2011 Microchip Technology Inc. PIC12(L)F1840 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2 ...
Page 90
... SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP OST (3) T Interrupt Latency (4) Processor in Sleep Inst( Dummy Cycle Inst( Preliminary 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) 2011 Microchip Technology Inc. ...
Page 91
... Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as ‘1’. Maintain this bit set. PIC12F1840 only. Note 1: 2011 Microchip Technology Inc. PIC12(L)F1840 9.2.2 PERIPHERAL USAGE IN SLEEP Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected ...
Page 92
... WDTPS4 WDTPS3 WDTPS2 WDTPS1 Preliminary Register Bit 1 Bit 0 on Page INTF IOCIF 83 IOCAF1 IOCAF0 120 IOCAN1 IOCAN0 120 IOCAP1 IOCAP0 120 TMR2IE TMR1IE 84 — — 85 TMR2IF TMR1IF 86 — — VREGPM Reserved 91 WDTPS0 SWDTEN 95 2011 Microchip Technology Inc. ...
Page 93
... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2011 Microchip Technology Inc. PIC12(L)F1840 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41441B-page 93 ...
Page 94
... Active event. See Section 3.0 “Memory Organization” Active The STATUS register information. Disabled Active Disabled Disabled Preliminary Section 5.0 “Oscillator for more and (Register 3-1) for more WDT Cleared Cleared until the end of OST Unaffected 2011 Microchip Technology Inc. ...
Page 95
... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. 2011 Microchip Technology Inc. R/W-1/1 R/W-0/0 R/W-1/1 WDTPS3 WDTPS2 WDTPS1 U = Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...
Page 96
... PIC12(L)F1840 NOTES: DS41441B-page 96 Preliminary 2011 Microchip Technology Inc. ...
Page 97
... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2011 Microchip Technology Inc. PIC12(L)F1840 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...
Page 98
... CPU is able to read and write data to the data EEPROM recommended to code-protect the pro- gram memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. Preliminary 2011 Microchip Technology Inc. (Register 4-1) ...
Page 99
... FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) INSTR( BSF EECON1,RD executed here executed here RD bit EEDATH EEDATL Register EERHLT 2011 Microchip Technology Inc. PIC12(L)F1840 EEADRH,EEADRL PC+3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( ...
Page 100
... NOPs. This prevents the user from executing a two-cycle instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit. Number of Boundary 32 words, = 00000 Preliminary instruction on the next 2011 Microchip Technology Inc. ...
Page 101
... NOP ; Executed NOP ; Ignored BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2011 Microchip Technology Inc. PIC12(L)F1840 (Figure 11-1) (Figure 11-1) Preliminary DS41441B-page 101 ...
Page 102
... However, the entire write latch block will be written to program memory. An example of the complete write sequence for 32 words is shown in Example loaded into the EEADRH:EEADRL register pair; the 32 words of data are loaded using indirect addressing. Preliminary 2011 Microchip Technology Inc. 11-5. The initial address is ...
Page 103
... EEADRL<4:0> = 00000 EEADRL<4:0> = 00001 Buffer Register 2011 Microchip Technology Inc. continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...
Page 104
... Write AAh ; Set WR bit to begin erase ; Any instructions here are ignored as processor ; halts to begin erase sequence ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2011 Microchip Technology Inc. ...
Page 105
... EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2011 Microchip Technology Inc. PIC12(L)F1840 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...
Page 106
... Table When read access is initiated on an address outside the parameters listed in register pair is cleared. Function Read Access User IDs Yes Yes Yes Figure 11-1) Figure 11-1) Preliminary 11-2. Table 11-2, the EEDATH:EEDATL Write Access Yes No No 2011 Microchip Technology Inc. ...
Page 107
... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue 2011 Microchip Technology Inc. PIC12(L)F1840 Preliminary DS41441B-page 107 ...
Page 108
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 EEADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0 2011 Microchip Technology Inc. ...
Page 109
... RD: Read Control bit 1 = Initiates a program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read. 2011 Microchip Technology Inc. PIC12(L)F1840 R/W/HC-0/0 R/W-x/q R/W-0/0 ...
Page 110
... WREN EEADRL<7:0> EEADRH<6:0 EEDATL<7:0> EEDATH<5:0> INTE IOCIE TMR0IF EEIE BCL1IE — EEIF BCL1IF — Preliminary W-0/0 W-0/0 bit 0 Register Bit 1 Bit 0 on Page WR RD 109 110* 108 108 108 108 INTF IOCIF 83 — — 85 — — 87 2011 Microchip Technology Inc. ...
Page 111
... Write PORTA CK Data Register Data Bus Read PORTA To peripherals ANSELA 2011 Microchip Technology Inc. PIC12(L)F1840 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register ...
Page 112
... CCP1SEL: Pin Selection bit 0 = CCP1/P1A function is on RA2 1 = CCP1/P1A function is on RA5 DS41441B-page 112 U-0 R/W-0/0 R/W-0/0 T1GSEL TXCKSEL — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 P1BSEL CCP1SEL bit 0 ...
Page 113
... CLRF PORTA ;Init PORTA BANKSEL LATA ;Data Latch CLRF LATA ; BANKSEL ANSELA ; CLRF ANSELA ;digital I/O BANKSEL TRISA ; MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA ;and set RA<2:0> as ;outputs 2011 Microchip Technology Inc. 12-2) reads the Preliminary PIC12(L)F1840 DS41441B-page 113 ...
Page 114
... ICDCLK 3. SCL 4. RX/DT (EUSART) 5. SCK RA2 1. SRQ 2. C1OUT (Comparator) 3. SDA 4. CCP1/P1A DS41441B-page 114 RA3 No output priorities. Input only pin. RA4 1. OSC2 2. CLKOUT 3. T1OSO 4. CLKR 5. TX/CK 6. SDO 7. P1B RA5 1. OSC1 2. T1OSI (Timer1 Oscillator) 3. SRNQ 4. RX/DT 5. CCP1/P1A Preliminary 2011 Microchip Technology Inc. ...
Page 115
... TRISA3: RA3 Port Tri-State Control bit This bit is always ‘1’ as RA3 is an input only bit 2-0 TRISA<2:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated PORTA pin configured as an output 2011 Microchip Technology Inc. PIC12(L)F1840 R/W-x/x R-x/x R/W-x/x RA4 ...
Page 116
... R/W-1/1 ANSA4 — ANSA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. (1) . Digital input buffer disabled. Preliminary R/W-x/u R/W-x/u LATA1 LATA0 bit 0 R/W-1/1 R/W-1/1 ANSA1 ANSA0 bit 0 2011 Microchip Technology Inc. ...
Page 117
... CONFIG1 7:0 CP MCLRE — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. Legend: 2011 Microchip Technology Inc. R/W-1/1 R/W-1/1 R/W-1/1 WPUA4 WPUA3 WPUA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 118
... PIC12(L)F1840 NOTES: DS41441B-page 118 Preliminary 2011 Microchip Technology Inc. ...
Page 119
... R RAx IOCAPx 2011 Microchip Technology Inc. PIC12(L)F1840 13.3 Interrupt Flags The IOCAFx bits located in the IOCAF register are status flags that correspond to the Interrupt-on-change pins of PORTA expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set ...
Page 120
... R/W/HS-0/0 IOCAF4 IOCAF3 IOCAF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware Preliminary R/W-0/0 R/W-0/0 IOCAP1 IOCAP0 bit 0 R/W-0/0 R/W-0/0 IOCAN1 IOCAN0 bit 0 R/W/HS-0/0 R/W/HS-0/0 IOCAF1 IOCAF0 bit 0 2011 Microchip Technology Inc. ...
Page 121
... IOCAN — — IOCAP — — TRISA — — Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change. 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 — ANSA2 TMR0IE INTE IOCIE TMR0IF ...
Page 122
... PIC12(L)F1840 NOTES: DS41441B-page 122 Preliminary 2011 Microchip Technology Inc. ...
Page 123
... FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY 2011 Microchip Technology Inc. 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, DAC and CPS module is routed through two independent programmable gain amplifiers. Each , with 1.024V, ...
Page 124
... Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) (High Range) (Low Range Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR1 CDAFVR0 Preliminary R/W-0/0 R/W-0/0 ADFVR1 ADFVR0 bit 0 (2) (2) (2) (2) Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 124 2011 Microchip Technology Inc. ...
Page 125
... The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2011 Microchip Technology Inc. FIGURE 15-1: 15.2 Minimum Operating V Minimum Sensing Temperature ...
Page 126
... PIC12(L)F1840 NOTES: DS41441B-page 126 Preliminary 2011 Microchip Technology Inc. ...
Page 127
... AN3 Temp Indicator DAC FVR Buffer1 CHS<4:0> Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2011 Microchip Technology Inc. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) allows ADPREF = 00 ...
Page 128
... ADC clock selections. Unless using the F Note: system clock frequency will change the ADC adversely affect the ADC result. Section 16.2 Preliminary AD Figure 16-2. specifica- AD Table 16-1 gives examples of , any changes in the RC clock frequency, which may 2011 Microchip Technology Inc. ...
Page 129
... Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2011 Microchip Technology Inc DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 20 MHz 16 MHz (2) 100 ns (2) 125 ns (2) (2) (2) (2) 200 ns 250 ns (2) (2) 0.5 ...
Page 130
... ADCON1 register controls the output format. Figure 16-3 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 2011 Microchip Technology Inc. ...
Page 131
... A device Reset forces all registers to their Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2011 Microchip Technology Inc. PIC12(L)F1840 16.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 132
... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space 2011 Microchip Technology Inc. ...
Page 133
... See Section 17.0 “Digital-to-Analog Converter (DAC) Module” for more information. Note 1: See 2: Section 14.0 “Fixed Voltage Reference (FVR)” See 3: Section 15.0 “Temperature Indicator Module” 2011 Microchip Technology Inc. PIC12(L)F1840 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (3) ...
Page 134
... R/W-0/0 U-0 U-0 — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets DD (1) pin REF + pin as the source of the positive reference, be aware that a REF Preliminary R/W-0/0 R/W-0/0 ADPREF<1:0> bit 0 (1) 2011 Microchip Technology Inc. ...
Page 135
... Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2011 Microchip Technology Inc. PIC12(L)F1840 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 136
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES<9:8> bit 0 R/W-x/u R/W-x/u bit 0 2011 Microchip Technology Inc. ...
Page 137
... The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2011 Microchip Technology Inc. source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...
Page 138
... V - REF DS41441B-page 138 V DD Sampling Switch 0. Rss R IC LEAKAGE (1) I 0. Full-Scale Range 0.5 LSB Zero-Scale Full-Scale Transition V REF Transition Preliminary HOLD REF Sampling Switch (k) Analog Input Voltage 1.5 LSB + 2011 Microchip Technology Inc. ...
Page 139
... PEIE PIE1 TMR1GIE ADIE PIR1 TMR1GIF ADIF TRISA — — — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Legend: 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 CHS3 CHS2 CHS1 CHS0 ADCS1 ADCS0 — — ...
Page 140
... PIC12(L)F1840 NOTES: DS41441B-page 140 Preliminary 2011 Microchip Technology Inc. ...
Page 141
... The value of the individual resistors within the ladder can be found in Section 30.0 Specifications”. 2011 Microchip Technology Inc. 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. The DAC output voltage is determined by the following equations: ...
Page 142
... VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41441B-page 142 Digital-to-Analog Converter (DAC) V SOURCE + Steps SOURCE - + DACOUT – Preliminary DACR<4:0> 5 DAC (To Comparator, CPS and ADC Modules) DACOUT DACOE Buffered DAC Output 2011 Microchip Technology Inc. ...
Page 143
... DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared. 2011 Microchip Technology Inc. This is also the method used to output the voltage level from the FVR to an output pin. See “Operation During Sleep” ...
Page 144
... Bit 2 TSEN TSRNG CDAFVR1 CDAFVR0 DACOE — DACPSS1 DACPSS0 — DACR4 DACR3 DACR2 Preliminary U-0 R/W-0/0 — DACNSS bit 0 R/W-0/0 R/W-0/0 bit 0 Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 124 — — 144 DACR1 DACR0 144 2011 Microchip Technology Inc. ...
Page 145
... The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs. Both of the SR Latch outputs may be directly output to an I/O pin at the same time. 2011 Microchip Technology Inc. PIC12(L)F1840 The applicable TRIS bit of the corresponding port must be cleared to enable the port pin output driver. ...
Page 146
... Gen SRI SRRPE SRCLK SRRCKE (3) SYNCC1OUT SRRC1E and simultaneously Note 1: Pulse generator causes a 1 Q-state pulse width. 2: Name denotes the connection point at the comparator output. 3: DS41441B-page 146 SRLEN SRQEN (1) Latch R Q SRLEN SRNQEN Preliminary 2011 Microchip Technology Inc. SRQ SRNQ ...
Page 147
... Pulse set input for 1 Q-clock period effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse reset input for 1 Q-clock period effect on Reset input. Set only, always reads back ‘0’. Note 1: 2011 Microchip Technology Inc MHz MHz OSC OSC 39.0 kHz 31 ...
Page 148
... C1 Comparator output has no effect on the reset input of the SR Latch DS41441B-page 148 R/W-0/0 R/W-0/0 R/W-0/0 SRSC1E SRRPE SRRCKE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 Reserved SRRC1E bit 0 2011 Microchip Technology Inc. ...
Page 149
... Bit 7 Bit 6 SRCON0 SRLEN SRCLK2 SRCON1 SRSPE SRSCKE TRISA — — — = unimplemented, read as ‘0’. Shaded cells are unused by the SR Latch module. Legend: 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 SRCLK1 SRCLK0 SRQEN SRNQEN Reserved SRSC1E SRRPE SRRCKE ...
Page 150
... PIC12(L)F1840 NOTES: DS41441B-page 150 Preliminary 2011 Microchip Technology Inc. ...
Page 151
... When the analog voltage at V less than the analog voltage the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN 2011 Microchip Technology Inc. PIC12(L)F1840 FIGURE 19- ...
Page 152
... Output of comparator can be frozen during debugging. 3: DS41441B-page 152 (1) Interrupt Interrupt C1POL D ( (from Timer1) T1CLK Preliminary C1INTP det Set C1IF C1INTN det C1OUT To Data Bus Q MC1OUT To ECCP PWM Logic C1SYNC C1OE TRIS bit C1OUT Timer1 or SR Latch SYNCC1OUT 2011 Microchip Technology Inc. ...
Page 153
... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 2011 Microchip Technology Inc. 19.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The ...
Page 154
... Section 14.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section 17.0 “Digital-to-Analog for more information on the DAC input (DAC) Module” signal. Any time the comparator is disabled (C1ON = 0), all comparator inputs are disabled. Preliminary 2011 Microchip Technology Inc. Converter ...
Page 155
... ECCP Auto-Shutdown mode. 2011 Microchip Technology Inc. PIC12(L)F1840 19.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 19-3 ...
Page 156
... Input Capacitance PIN I = Leakage Current at the pin due to various junctions LEAKAGE R = Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See Section 30.0 “Electrical Specifications”. DS41441B-page 156 V DD 0. (1) LEAKAGE 0. Vss Preliminary To Comparator 2011 Microchip Technology Inc. ...
Page 157
... C1SYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous. 2011 Microchip Technology Inc. PIC12(L)F1840 R/W-0/0 U-0 R/W-1/1 ...
Page 158
... U-0 R-0/0 MC1OUT — — bit 0 Register Bit 1 Bit 0 on Page ANSA1 ANSA0 116 C1HYS C1SYNC 157 — — C1NCH 158 — — MC1OUT 158 INTF IOCIF 83 — — — 85 — — — 87 TRISA1 TRISA0 115 2011 Microchip Technology Inc. ...
Page 159
... From CPSCLK 1 TMR0SE TMR0CS T0XCS 2011 Microchip Technology Inc. PIC12(L)F1840 20.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION register to ‘ ...
Page 160
... Section 30.0 “Electrical Specifications”. 20.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41441B-page 160 Preliminary 2011 Microchip Technology Inc. ...
Page 161
... Timer0 Module Register TRISA — — Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. 2011 Microchip Technology Inc. R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 162
... PIC12(L)F1840 NOTES: DS41441B-page 162 Preliminary 2011 Microchip Technology Inc. ...
Page 163
... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2011 Microchip Technology Inc. • Gate Toggle Mode • Gate Single-pulse Mode • Gate Value Status • Gate Event Interrupt Figure 21 block diagram of the Timer1 module ...
Page 164
... T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. T1OSCEN System Clock (F ) OSC x Instruction Clock (F OSC x Capacitive Sensing Oscillator x External Clocking on T1CKI Pin 0 Osc.Circuit On T1OSI/T1OSO Pins 1 Preliminary internal clock source is selected, the system clock or they can run Clock Source /4) 2011 Microchip Technology Inc. ...
Page 165
... A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 2011 Microchip Technology Inc. PIC12(L)F1840 21.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry ...
Page 166
... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared). Preliminary Figure 21-6 for timing 2011 Microchip Technology Inc. ...
Page 167
... T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2011 Microchip Technology Inc. PIC12(L)F1840 21.9 ECCP/CCP Capture/Compare Time Base The CCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...
Page 168
... PIC12(L)F1840 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41441B-page 168 Preliminary 2011 Microchip Technology Inc ...
Page 169
... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2011 Microchip Technology Inc. PIC12(L)F1840 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41441B-page 169 ...
Page 170
... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41441B-page 170 Set by hardware on falling edge of T1GVAL Preliminary 2011 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Cleared by software ...
Page 171
... This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop 2011 Microchip Technology Inc. PIC12(L)F1840 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ...
Page 172
... Comparator 1 optionally synchronized output (SYNCC1OUT Reserved DS41441B-page 172 R/W-0/u R/W/HC-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware Preliminary R/W-0/u R/W-0/u T1GSS<1:0> bit 0 2011 Microchip Technology Inc. ...
Page 173
... TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T1CON TMR1GE T1GPOL T1GCON Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 — ANSA2 ...
Page 174
... PIC12(L)F1840 NOTES: DS41441B-page 174 Preliminary 2011 Microchip Technology Inc. ...
Page 175
... Optional use as the shift clock for the MSSP1 modules See Figure 22-1 for a block diagram of Timer2. FIGURE 22-1: TIMER2 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 T2CKPS<1:0> 2011 Microchip Technology Inc. PIC12(L)F1840 TMR2 Output Reset TMR2 Postscaler Comparator 1 PR2 T2OUTPS<3:0> Preliminary ...
Page 176
... SSP (MSSP1) Module Overview” 22.4 Timer2 Operation During Sleep Timer2 cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and PR2 the output registers will remain unchanged while the processor is “Timer2 in Sleep mode. Preliminary 2011 Microchip Technology Inc. ...
Page 177
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler Prescaler is 64 2011 Microchip Technology Inc. PIC12(L)F1840 R/W-0/0 R/W-0/0 R/W-0/0 TMR2ON U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary ...
Page 178
... Bit 3 Bit 2 DC1B<1:0> TMR0IE INTE IOCIE TMR0IF RCIE TXIE SSP1IE CCP1IE RCIF TXIF SSP1IF CCP1IF T2OUTPS<3:0> TMR2ON T2CKPS1 T2CKPS0 Preliminary Register Bit 1 Bit 0 on Page CCP1M<3:0> 207 INTF IOCIF 83 TMR2IE TMR1IE 84 TMR2IF TMR1IF 86 175* 177 175* 2011 Microchip Technology Inc. ...
Page 179
... No Channel * MDCLPOL Selected * 1111 2011 Microchip Technology Inc. Using this method, the DSM can generate the following types of Key Modulation schemes: • Frequency-Shift Keying (FSK) • Phase-Shift Keying (PSK) • On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: • ...
Page 180
... MDCHSYNC bit in the MDCARH register. Synchroniza- tion for the carrier low signal can be enabled by setting the MDCLSYNC bit in the MDCARL register. Figure 23-1 through Figure 23-5 of using various synchronization methods. Preliminary 2011 Microchip Technology Inc. show timing diagrams ...
Page 181
... Active Carrier State FIGURE 23-3: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 CARH Active Carrier State 2011 Microchip Technology Inc. PIC12(L)F1840 CARL CARH CARH CARL both Preliminary CARL both CARL DS41441B-page 181 ...
Page 182
... Active Carrier CARH State FIGURE 23-5: FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier CARH State DS41441B-page 182 CARL CARH CARL CARH Preliminary 2011 Microchip Technology Inc. CARL CARL ...
Page 183
... Slew Rate Control The slew rate limitation on the output port pin can be disabled. The slew rate limitation can be removed by clearing the MDSLR bit in the MDCON register. 2011 Microchip Technology Inc. PIC12(L)F1840 23.11 Operation in Sleep Mode The Data Signal Modulator (DSM) module is not affected by Sleep mode ...
Page 184
... MDBIT must be selected as the modulation source in the MDSRC register for this operation. 2: DS41441B-page 184 R/W-0/0 R-0/0 U-0 MDOPOL MDOUT — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary U-0 R/W-0/0 — MDBIT bit 0 (1) 2011 Microchip Technology Inc. ...
Page 185
... CCP1 output (PWM Output mode only) 0001 = MDMIN port pin 0000 = MDBIT bit of MDCON register is modulation source Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. Note 1: 2011 Microchip Technology Inc. PIC12(L)F1840 U-0 R/W-x/u R/W-x/u — ...
Page 186
... Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. Note 1: DS41441B-page 186 U-0 R/W-x/u R/W-x/u — MDCH<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary 2011 Microchip Technology Inc. R/W-x/u R/W-x/u bit 0 (1) ...
Page 187
... MDOE MDSRC MDMSODIS — — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode. Legend: 2011 Microchip Technology Inc. U-0 R/W-x/u — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 188
... PIC12(L)F1840 NOTES: DS41441B-page 188 Preliminary 2011 Microchip Technology Inc. ...
Page 189
... This device contains one Enhanced Capture/Compare/ PWM module (ECCP1). The Half-Bridge ECCP module has two available I/O pins. See Table 24-1. TABLE 24-1: PWM RESOURCES Device Name ECCP1 PIC12(L)F1840 Enhanced PWM Half-Bridge 2011 Microchip Technology Inc. PIC12(L)F1840 Preliminary DS41441B-page 189 ...
Page 190
... CCP1CON Preliminary /4) or from an OSC of the CCP1CON register. demonstrates the code to CHANGING BETWEEN CAPTURE PRESCALERS ;Set Bank bits to point ;to CCP1CON ;Turn CCP1 module off ;the new prescaler ;move value and CCP1 ON ;Load CCP1CON with this ;value 2011 Microchip Technology Inc. ...
Page 191
... TRISA5 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode. * Page provides register information. 2011 Microchip Technology Inc. 24.1.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON ...
Page 192
... Since F OSC down during Sleep mode, the Compare mode will not function properly during Sleep. Preliminary ) should not be used in Capture OSC /4) or from an OSC the match condition by the Timer1 Reset, will is shut OSC 2011 Microchip Technology Inc. ...
Page 193
... Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TRISA — — TRISA5 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode. * Page provides register information. 2011 Microchip Technology Inc. for Bit 5 Bit 4 Bit 3 Bit 2 T1GSEL TXCKSEL — ...
Page 194
... PR2 The 8-bit timer TMR2 register is concatenated Note 1: with the 2-bit internal system clock (F 2 bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPR1H is a read-only register. 2: Preliminary 2011 Microchip Technology Inc. TMR2 = PR2 CCP1CON<5:4> CCP1 TRIS ), or OSC ...
Page 195
... Prescale Value 1/F Note 1: OSC OSC 2011 Microchip Technology Inc. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • ...
Page 196
... PR2 + 1 ----------------------------------------- - bits 2 log = 32 MHz) 250 kHz 333.3 kHz 1 1 0x1F 0x17 7 6 MHz) 156.3 kHz 208.3 kHz 1 1 0x1F 0x17 7 6 MHz) 153.85 kHz 200.0 kHz 1 1 0x0C 0x09 5 5 2011 Microchip Technology Inc. ...
Page 197
... Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information. 2011 Microchip Technology Inc. 24.3.9 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON ...
Page 198
... PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal. P1M<1:0> CCP1M<3:0> Output Controller CCP1/P1A Q TRISx P1B TRISx PWM1CON Preliminary the generation of an CCP1/P1A P1B 2011 Microchip Technology Inc. ...
Page 199
... P1A Modulated (Half-Bridge) 10 P1B Modulated Relationships: • Period = (PR2 + 1) * (TMRx Prescale Value) OSC • Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMRx Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC 2011 Microchip Technology Inc. PIC12(L)F1840 P1M<1:0> CCP1/P1A (1) Yes 00 Yes 10 Pulse 0 Width Period Delay Delay ...
Page 200
... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FET Driver P1A Load FET Driver P1B V+ FET Driver Load FET Driver Preliminary EXAMPLE OF HALF- BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver 2011 Microchip Technology Inc. ...