PIC16F1507-E/ML Microchip Technology, PIC16F1507-E/ML Datasheet - Page 217

3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm TUBE

PIC16F1507-E/ML

Manufacturer Part Number
PIC16F1507-E/ML
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F1507-E/ML

Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
 Details
PIC16(L)F1507
MOVWI
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS41586A-page 217
Mode
Preincrement
Predecrement
Postincrement
Postdecrement
Move W to INDFn
[ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn]
n  [ 0 , 1 ]
mm  [ 00 , 01 , 10 , 11 ]
-32  k  31
W  INDFn
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
Unchanged
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to wrap
around.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
None
Syntax
FSRn++
FSRn--
++FSRn
--FSRn
mm
00
01
10
11
Preliminary
NOP
Syntax:
Operands:
Operation:
Status Affected:
Description:
Words:
Cycles:
Example:
OPTION
Syntax:
Operands:
Operation:
Status Affected:
Description:
RESET
Syntax:
Operands:
Operation:
Status Affected:
Description:
Load OPTION_REG Register
with W
[ label ] OPTION
None
(W)  OPTION_REG
None
Move data from W register to
OPTION_REG register.
Software Reset
[ label ] RESET
None
Execute a device Reset. Resets the
nRI flag of the PCON register.
None
This instruction provides a way to
execute a hardware Reset by soft-
ware.
No Operation
[ label ]
None
No operation
None
No operation.
1
1
NOP
 2011 Microchip Technology Inc.
NOP

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