PIC16F1507-E/P Microchip Technology, PIC16F1507-E/P Datasheet - Page 72

3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 PDIP .300in TUBE

PIC16F1507-E/P

Manufacturer Part Number
PIC16F1507-E/P
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 PDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F1507-E/P

Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Package / Case
PDIP-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
 Details
7.6.7
The PIR3 register contains the interrupt flag bits, as
shown in
REGISTER 7-7:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-2
bit 1
bit 0
U-0
Register
PIR3 REGISTER
Unimplemented: Read as ‘0’
CLC2IF: Configurable Logic Block 2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
CLC1IF: Configurable Logic Block 1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
7-7.
U-0
PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
U-0
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
U-0
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
U-0
PIC16(L)F1507
software
R/W-0/0
CLC2IF
should
DS41586A-page 72
ensure
R/W-0/0
CLC1IF
bit 0
the

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