PIC16F1507-I/ML Microchip Technology, PIC16F1507-I/ML Datasheet - Page 164

3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm TUBE

PIC16F1507-I/ML

Manufacturer Part Number
PIC16F1507-I/ML
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F1507-I/ML

Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F1507-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
20.1.5
The following steps should be followed when setting up
the CLCx:
• Disable CLCx by clearing the LCxEN bit.
• Select desired inputs using CLCxSEL0 and
• Clear any associated ANSEL bits.
• Set all TRIS bits associated with inputs.
• Clear all TRIS bits associated with outputs.
• Enable the chosen inputs through the four gates
• Select the gate output polarities with the LCx-
• Select the desired logic function with the
• Select the desired polarity of the logic output with
• If driving the CLCx pin, set the LCxOE bit of the
• If interrupts are desired, configure the following
• Enable the CLCx by setting the LCxEN bit of the
20.2
An interrupt will be generated upon a change in the
output value of the CLCx when the appropriate interrupt
enables are set. A rising edge detector and a falling
edge detector are present in each CLC for this purpose.
The LCxIF bit of the associated PIR registers will be set
when either edge detector is triggered and its associ-
ated enable bit is set. The LCxINTP enables rising
edge interrupts and the LCxINTN bit enables falling
edge interrupts. Both are located in the CLCxCON reg-
ister.
To fully enable the interrupt, set the following bits:
• LCxON bit of the CLCxCON register
• LCxIE bit of the associated PIE registers
• LCxINTP bit of the CLCxCON register (for a rising
• LCxINTN bit of the CLCxCON register (for a fall-
 2011 Microchip Technology Inc.
CLCxSEL1 registers (See
using CLCxGLS0, CLCxGLS1, CLCxGLS2, and
CLCxGLS3 registers.
POLy bits of the CLCxPOL register.
LCxMODE<2:0> bits of the CLCxCON register.
the LCxPOL bit of the CLCxPOL register. (This
step may be combined with the previous gate out-
put polarity step).
CLCxCON register and also clear the TRIS bit
corresponding to that output.
bits:
- Set the LCxINTP bit in the CLCxCON register
- Set the LCxINTN bit in the CLCxCON
- Set the CLCxIE bit of the associated PIE
- Set the GIE and PEIE bits of the INTCON
CLCxCON register.
edge detection)
ing edge detection)
for rising event.
register or falling event.
registers.
register.
CLCx Interrupts
CLCx SETUP STEPS
Table
20-1).
Preliminary
• PEIE and GIE bits of the INTCON register
The LCxIF bit of the associated PIR registers, must be
cleared in software as part of the interrupt service. If
another edge is detected while this flag is being
cleared, the flag will still be set at the end of the
sequence.
20.3
Mirror copies of all LCxCON output bits are contained
in the CLCxDATA register. Reading this register reads
the outputs of all CLCs simultaneously. This prevents
any reading skew introduced by testing or reading the
CLCxOUT bits in the individual CLCxCON registers.
20.4
The CLCxCON register is cleared to zero as the result
of a Reset. All other selection and gating values remain
unchanged.
20.5
The CLC module operates independently from the
system clock and will continue to run during Sleep,
provided that the input sources selected remain active.
The HFINTOSC remains active during Sleep when the
CLC module is enabled and the HFINTOSC is
selected as an input source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and as a CLC input
source, when the CLC is enabled, the CPU will go idle
during Sleep, but the CLC will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
Output Mirror Copies
Effects of a Reset
Operation During Sleep
PIC16(L)F1507
DS41586A-page 164

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