PIC16F1507-I/SS Microchip Technology, PIC16F1507-I/SS Datasheet - Page 142

3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SSOP .209in TUBE

PIC16F1507-I/SS

Manufacturer Part Number
PIC16F1507-I/SS
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F1507-I/SS

Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SSOP-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
 Details

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Part Number:
PIC16F1507-I/SS
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PIC16F1507-I/SS
0
17.5.2.1
The T1G pin is one source for Timer1 Gate Control. It
can be used to supply an external source to the Timer1
gate circuitry.
17.5.2.2
When Timer0 increments from FFh to 00h, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
17.5.3
When Timer1 Gate Toggle mode is enabled, it is possi-
ble to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the sig-
nal. See
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
17.5.4
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next incrementing
edge. On the next trailing edge of the pulse, the
T1GGO/DONE bit will automatically be cleared. No other
gate events will be allowed to increment Timer1 until the
T1GGO/DONE bit is once again set in software. See
Figure 17-5
If the Single Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1 gate
source to be measured. See
details.
 2011 Microchip Technology Inc.
Note:
Figure 17-4
TIMER1 GATE TOGGLE MODE
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
TIMER1 GATE SINGLE-PULSE
MODE
for timing details.
T1G Pin Gate Operation
Timer0 Overflow Gate Operation
for timing details.
Figure 17-6
for timing
Preliminary
17.5.5
When Timer1 Gate Value Status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
17.5.6
When Timer1 Gate Event Interrupt is enabled, it is pos-
sible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
TIMER1 GATE VALUE STATUS
TIMER1 GATE EVENT INTERRUPT
PIC16(L)F1507
DS41586A-page 142

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