PIC16F1507T-I/ML Microchip Technology, PIC16F1507T-I/ML Datasheet - Page 113

3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm T/R

PIC16F1507T-I/ML

Manufacturer Part Number
PIC16F1507T-I/ML
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm T/R
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F1507T-I/ML

Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
 Details
PIC16(L)F1507
12.6
REGISTER 12-1:
REGISTER 12-2:
REGISTER 12-3:
DS41586A-page 113
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5-0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5-0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5-0
U-0
U-0
U-0
Interrupt-On-Change Registers
Unimplemented: Read as ‘ 0 ’
IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge.
0 = Interrupt-on-Change disabled for the associated pin.
Unimplemented: Read as ‘ 0 ’
IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge.
0 = Interrupt-on-Change disabled for the associated pin.
Unimplemented: Read as ‘ 0 ’
IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits
1 = An enabled change was detected on the associated pin.
0 = No change was detected, or the user cleared the detected change.
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was
detected on RAx.
upon detecting an edge.
upon detecting an edge.
U-0
U-0
U-0
IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W/HS-0/0
R/W-0/0
IOCAP5
R/W-0/0
IOCAN5
IOCAF5
R/W/HS-0/0
R/W-0/0
IOCAP4
R/W-0/0
IOCAN4
IOCAF4
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS - Bit is set in hardware
R/W/HS-0/0
IOCAP3
IOCAN3
R/W-0/0
R/W-0/0
IOCAF3
R/W/HS-0/0
R/W-0/0
IOCAP2
R/W-0/0
IOCAN2
IOCAF2
IOCAFx bit and IOCIF
IOCAFx bit and IOCIF
 2011 Microchip Technology Inc.
R/W/HS-0/0
IOCAN1
R/W-0/0
IOCAP1
R/W-0/0
IOCAF1
flag will be set
flag will be set
R/W/HS-0/0
R/W-0/0
IOCAP0
R/W-0/0
IOCAN0
IOCAF0
bit 0
bit 0
bit 0

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