PIC16F1507T-I/ML Microchip Technology, PIC16F1507T-I/ML Datasheet - Page 156

3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm T/R

PIC16F1507T-I/ML

Manufacturer Part Number
PIC16F1507T-I/ML
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm T/R
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F1507T-I/ML

Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
 Details
19.1
All PWM outputs are multiplexed with the PORT data
latch. The user must configure the pins as outputs by
clearing the associated TRIS bits.
19.1.1
The PWM module produces a 10-bit resolution output.
Timer2 and PR2 set the period of the PWM. The
PWMxDCL and PWMxDCH registers configure the
duty cycle. The period is common to all PWM modules,
whereas the duty cycle is independently controlled.
All PWM outputs associated with Timer2 are set when
TMR2 is cleared. Each PWMx is cleared when TMR2
is equal to the value specified in the corresponding
PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) reg-
isters. When the value is greater than or equal to PR2,
the PWM output is never cleared (100% duty cycle).
19.1.2
The output polarity is inverted by setting the PWMxPOL
bit of the PWMxCON register.
19.1.3
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of
EQUATION 19-1:
 2011 Microchip Technology Inc.
Note:
Note:
Note:
Note:
PWM Period
PWMx Pin Configuration
Equation
Clearing the PWMxOE bit will relinquish
control of the PWMx pin.
FUNDAMENTAL OPERATION
The Timer2 postscaler is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
The PWMxDCH and PWMxDCL registers
are double buffered. The buffers are
updated when Timer2 matches PR2. Care
should be taken to update both registers
before the timer match occurs.
PWM OUTPUT POLARITY
PWM PERIOD
T
OSC
=
19-1.
= 1/F
(TMR2 Prescale Value)
PWM PERIOD
PR2
OSC
+
1
 4 T
OSC
Preliminary
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The PWM output is active. (Exception: When the
• The PWMxDCH and PWMxDCL register values
19.1.4
The PWM duty cycle is specified by writing a 10-bit
value to the PWMxDCH and PWMxDCL register pair.
The PWMxDCH register contains the eight MSbs and
the PWMxDCL<7:6>, the two LSbs. The PWMxDCH
and PWMxDCL registers can be written to at any time.
Equation 19-2
width.
Equation 19-3
ratio.
EQUATION 19-2:
EQUATION 19-3:
The 8-bit timer TMR2 register is concatenated with the
two Least Significant bits of 1/F
Timer2 prescaler to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to
1:1.
PWM duty cycle = 0%, the PWM output will
remain inactive.)
are latched into the buffers.
Note:
Duty Cycle Ratio
Note: T
Pulse Width
The Timer2 postscaler has no effect on
the PWM operation.
PWM DUTY CYCLE
OSC
is used to calculate the PWM duty cycle
is used to calculate the PWM pulse
= 1/F
PIC16(L)F1507
=
=
PWMxDCH:PWMxDCL<7:6>
OSC
---------------------------------------------------------------------------------- -
T
PWMxDCH:PWMxDCL<7:6>
PULSE WIDTH
DUTY CYCLE RATIO
OS C
4 PR2
(TMR2 Prescale Value)
OSC
DS41586A-page 156
+
, adjusted by the
1

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