PIC16F1829-E/P Microchip Technology, PIC16F1829-E/P Datasheet - Page 101

14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P

PIC16F1829-E/P

Manufacturer Part Number
PIC16F1829-E/P
Description
14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet

Specifications of PIC16F1829-E/P

Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC16F182x
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
18
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8.5.9
The PIR4 register contains the interrupt flag bits, as
shown in
REGISTER 8-9:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 1
bit 0
Note 1:
U-0
Register
This register is only available on PIC16F/LF1829.
PIR4 REGISTER
Unimplemented: Read as ‘0’
BCL2IF: MSSP2 Bus Collision Interrupt Flag bit
1 = A Bus Collision was detected (must be cleared in software)
0 = No Bus collision was detected
SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit
1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software)
0 = Waiting to Transmit/Receive/Bus Condition in progress
8-9.
U-0
PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4
(1)
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
U-0
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware
U-0
PIC16F/LF1825/1829
Note 1: The PIR4 register is available only on the
2: Interrupt flag bits are set when an inter-
PIC16F/LF1829 device.
rupt condition occurs, regardless of the
state of its corresponding enable bit or
the Global Enable bit, GIE, of the
INTCON register. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
U-0
(1)
R/W/HS-0/0
BCL2IF
DS41440A-page 101
R/W/HS-0/0
SSP2IF
bit 0

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