PIC16F1829-E/P Microchip Technology, PIC16F1829-E/P Datasheet - Page 187

• Manufacturer Part Number: PIC16F1829-E/P
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ mTouch™ 16Fr

Specifications of PIC16F1829-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC16F182x
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 20-1:
TABLE 20-1:
 2010 Microchip Technology Inc.
CPSCON0
FVRCON
INLVLA
INTCON
OPTION_REG
TMR0
TRISA
Legend:
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
R/W-1/1
WPUEN
Name
*
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
Page provides register information.
Timer0 Module Register
WPUEN: Weak Pull-up Enable bit
1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
TMR0CS: Timer0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (F
TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
CPSON
WPUEN
FVREN
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
INTEDG
R/W-1/1
Bit 7
GIE
—
—
OPTION_REG: OPTION REGISTER
Bit Value
FVRRDY
INTEDG
CPSRM
000
001
010
011
100
101
110
111
PEIE
Bit 6
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
—
—
TMR0CS
R/W-1/1
Timer0 Rate
TMR0CS
INLVLA5
TMR0IE
TRISA5
TSEN
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit 5
—
TMR0SE
R/W-1/1
TMR0SE
INLVLA4
TSRNG
TRISA4
Preliminary
INTE
Bit 4
—
OSC
/4)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
CPSRNG1
R/W-1/1
INLVLA3
TRISA3
IOCIE
Bit 3
PSA
PSA
PIC16F/LF1825/1829
CDAFVR<1:0>
CPSRNG0
INLVLA2
TMR0IF
TRISA2
Bit 2
R/W-1/1
PS<2:0>
CPSOUT
INLVLA1
TRISA1
Bit 1
INTF
ADFVR<1:0>
PS<2:0>
R/W-1/1
INLVLA0
TRISA0
T0XCS
IOCIF
Bit 0
DS41440A-page 189
R/W-1/1
Register
on Page
187*
333
148
131
189
129
93
bit 0