PIC16F1829-E/P Microchip Technology, PIC16F1829-E/P Datasheet - Page 223

14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P

PIC16F1829-E/P

Manufacturer Part Number
PIC16F1829-E/P
Description
14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet

Specifications of PIC16F1829-E/P

Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC16F182x
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
18
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
24.3.7
In Sleep mode, the TMRx register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMRx will continue from its
previous state.
24.3.8
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)”
24.3.9
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
TABLE 24-8:
 2010 Microchip Technology Inc.
APFCON1
CCP1CON
CCP2CON
CCP3CON
CCP4CON
CCPTMRS
CCPR1L
INLVLA
INLVLC
INTCON
PIE1
PIE2
PIE3
PIR1
PIR2
PIR3
PRx
T2CON
T4CON
T6CON
TMRx
TRISA
TRISC
Legend:
Note
Name
1:
2:
*
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
Applies to ECCP modules only.
PIC16F/LF1829 only.
Page provides register information.
OPERATION IN SLEEP MODE
CHANGES IN SYSTEM CLOCK
FREQUENCY
EFFECTS OF RESET
Capture/Compare/PWM Register x Low Byte (LSB)
Timer2/4/6 Period Register
Timer2/4/6 Module Register
INLVLC7
TRISC7
TMR1GIE
TMR1GIF
OSFIE
OSFIF
Bit 7
GIE
for additional details.
SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
C4TSEL<1:0>
P1M<1:0>
P2M<1:0>
(2)
(2)
INLVLC6
TRISC6
(1)
(1)
PEIE
ADIE
ADIF
Bit 6
C2IE
C2IF
(2)
(2)
SDO2SEL
INLVLA5
INLVLC5
TMR0IE
CCP4IE
CCP4IF
TRISA5
TRISC5
RCIE
RCIF
Bit 5
C1IE
C1IF
T2OUTPS<3:0>
T4OUTPS<3:0>
T6OUTPS<3:0>
C3TSEL<1:0>
DC1B<1:0>
DC2B<1:0>
DC3B<1:0>
DC4B<1:0>
(2)
SS2SEL
INLVLA4
INLVLC4
CCP3IE
CCP3IF
TRISC4
Preliminary
TRISA4
Bit 4
INTE
TXIE
EEIE
TXIF
EEIF
(2)
INLVLC3
P1DSEL
INLVLA3
TMR6IE
TMR6IF
SSP1IE
BCL1IE
SSP1IF
TRISA3
TRISC3
BCL1IF
24.3.10
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
registers, APFCON0 and APFCON1. To determine
which pins can be moved and what their default loca-
tions are upon a Reset, see
Pin Function”
IOCIE
Bit 3
PIC16F/LF1825/1829
C2TSEL<1:0>
TMR2ON
TMR4ON
TMR6ON
P1CSEL
INLVLA2
INLVLC2
TMR0IF
CCP1IE
CCP1IF
TRISA2
TRISC2
ALTERNATE PIN LOCATIONS
Bit 2
CCP1M<3:0>
CCP2M<3:0>
CCP3M<3:0>
CCP4M<3:0>
for more information.
INLVLA1
INLVLC1
P2BSEL
TMR2IE
TMR4IE
TMR2IF
TMR4IF
TRISC1
TRISA1
Bit 1
INTF
T2CKPS<1:0>
T4CKPS<1:0>
T6CKPS<1:0>
C1TSEL<1:0>
Section 12.1 “Alternate
CCP2SEL
INLVLC0
INLVLA0
TMR1IE
CCP2IE
TMR1IF
CCP2IF
TRISA0
TRISC0
IOCIF
DS41440A-page 225
Bit 0
Register on
Page
218*
203*
203*
126
240
240
240
240
241
131
142
100
205
205
205
129
140
93
94
95
96
98
99

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