PIC16F1829-E/P Microchip Technology, PIC16F1829-E/P Datasheet - Page 283

• Manufacturer Part Number: PIC16F1829-E/P
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ mTouch™ 16Fr

Specifications of PIC16F1829-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC16F182x
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 25-31:
25.6.10
While in Sleep mode, the I
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSPx interrupt is enabled).
25.6.11
A Reset disables the MSSPx module and terminates
the current transfer.
25.6.12
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSPx module is disabled. Control of the I
be taken when the P bit of the SSPxSTAT register is
set, or the bus is Idle, with both the S and P bits clear.
When the bus is busy, enabling the SSPx interrupt will
generate the interrupt when the Stop condition occurs.
In multi-master operation, the SDAx line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLxIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
 2010 Microchip Technology Inc.
Note: T
SLEEP OPERATION
EFFECTS OF A RESET
MULTI-MASTER MODE
SCLx
SDAx
Write to SSPxCON2,
Falling edge of
9th clock
BRG
= one Baud Rate Generator period.
STOP CONDITION RECEIVE OR TRANSMIT MODE
ACK
2
set PEN
C slave module can receive
T
T
BRG
BRG
SDAx asserted low before rising edge of clock
to setup Stop condition
2
C bus may
T
SCLx brought high after T
BRG
Preliminary
P
SCLx = 1 for T
after SDAx sampled high. P bit (SSPxSTAT<4>) is set.
T
BRG
25.6.13
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDAx pin, arbitration takes place when the master
outputs a ‘1’ on SDAx, by letting SDAx float high and
another master asserts a ‘0’. When the SCLx pin floats
high, data should be stable. If the expected data on
SDAx is a ‘1’ and the data sampled on the SDAx pin is
‘0’, then a bus collision has taken place. The master will
set the Bus Collision Interrupt Flag, BCLxIF and reset
the I
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDAx and SCLx lines are deasserted and
the SSPxBUF can be written to. When the user ser-
vices the bus collision Interrupt Service Routine and if
the I
tion by asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condi-
tion was in progress when the bus collision occurred, the
condition is aborted, the SDAx and SCLx lines are deas-
serted and the respective control bits in the SSPxCON2
register are cleared. When the user services the bus col-
lision Interrupt Service Routine and if the I
the user can resume communication by asserting a Start
condition.
The master will continue to monitor the SDAx and SCLx
pins. If a Stop condition occurs, the SSPxIF bit will be set.
A write to the SSPxBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I
can be taken when the P bit is set in the SSPxSTAT
register, or the bus is Idle and the S and P bits are
cleared.
PIC16F/LF1825/1829
PEN bit (SSPxCON2<2>) is cleared by
hardware and the SSPxIF bit is set
2
2
C port to its Idle state
C bus is free, the user can resume communica-
BRG
BRG
, followed by SDAx = 1 for T
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
(Figure
BRG
25-31).
DS41440A-page 285
2
C bus is free,
2
C bus