PIC16F1829-E/P Microchip Technology, PIC16F1829-E/P Datasheet - Page 29

• Manufacturer Part Number: PIC16F1829-E/P
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ mTouch™ 16Fr

Specifications of PIC16F1829-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC16F182x
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 3-4:
Legend:
40Ah
40Bh
40Ch
40Dh
40Eh
41Ah
41Bh
41Ch
41Dh
41Eh
400h
401h
402h
403h
404h
405h
406h
407h
408h
409h
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Fh
420h
46Fh
470h
47Fh
70h – 7Fh
BANK 8
Accesses
STATUS
PCLATH
INTCON
80 Bytes
General
Purpose
Register
T4CON
T6CON
FSR0L
FSR0H
FSR1L
FSR1H
WREG
INDF0
INDF1
TMR4
TMR6
BSR
PCL
PR4
PR6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
= Unimplemented data memory locations, read as ‘0’
PIC16F/LF1825/1829 MEMORY MAP, BANKS 8-15
48Ah
48Bh
48Ch
48Dh
48Eh
49Ah
49Bh
49Ch
49Dh
49Eh
4A0h
4EFh
4FFh
480h
481h
482h
483h
484h
485h
486h
487h
488h
489h
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Fh
4F0h
70h – 7Fh
BANK 9
Accesses
STATUS
PCLATH
INTCON
80 Bytes
General
Purpose
Register
FSR0L
FSR0H
FSR1L
FSR1H
WREG
INDF0
INDF1
BSR
PCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50Ah
50Bh
50Ch
50Dh
50Eh
51Ah
51Bh
51Ch
51Dh
51Eh
500h
501h
502h
503h
504h
505h
506h
507h
508h
509h
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Fh
520h
56Fh
570h
57Fh
BANK 10
70h – 7Fh
Accesses
STATUS
PCLATH
INTCON
80 Bytes
General
Purpose
Register
FSR0L
FSR0H
FSR1L
FSR1H
WREG
INDF0
INDF1
PCL
BSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
58Ah
58Bh
58Ch
58Dh
58Eh
58Fh
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
5EFh
5F0h
5FFh
580h
581h
582h
583h
584h
585h
586h
587h
588h
589h
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
BANK 11
70h – 7Fh
Accesses
STATUS
PCLATH
INTCON
Purpose
Register
80 Bytes
General
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
PCL
BSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
60Ah
60Bh
60Ch
60Dh
60Eh
60Fh
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
66Fh
67Fh
600h
601h
602h
603h
604h
605h
606h
607h
608h
609h
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
620h
670h
Unimplemented
Read as ‘0’
BANK 12
70h – 7Fh
Accesses
STATUS
PCLATH
INTCON
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
PCL
BSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
682h
685h
687h
688h
68Ah
68Bh
68Ch
68Dh
68Eh
68Fh
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
6EFh
6F0h
6FFh
680h
681h
683h
684h
686h
689h
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
Unimplemented
Read as ‘0’
BANK 13
70h – 7Fh
Accesses
STATUS
PCLATH
INTCON
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
PCL
BSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
700h
701h
702h
703h
704h
705h
706h
707h
708h
709h
70Ah
70Bh
70Ch
70Dh
70Eh
70Fh
710h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
76Fh
770h
77Fh
711h
Unimplemented
Read as ‘0’
BANK 14
70h – 7Fh
Accesses
STATUS
PCLATH
INTCON
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
PCL
BSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
780h
781h
782h
783h
784h
785h
786h
787h
788h
789h
78Ah
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7EFh
7F0h
7FFh
Unimplemented
Read as ‘0’
BANK 15
70h – 7Fh
Accesses
STATUS
PCLATH
INTCON
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
BSR
PCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—