PIC16F1829-E/P Microchip Technology, PIC16F1829-E/P Datasheet - Page 322

14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P

PIC16F1829-E/P

Manufacturer Part Number
PIC16F1829-E/P
Description
14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 P
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet

Specifications of PIC16F1829-E/P

Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC16F182x
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
18
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC16F/LF1825/1829
26.4.2
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART.
26.4.2.1
The operation of the Synchronous Master and Slave
modes
“Synchronous Master
case of the Sleep mode.
TABLE 26-9:
DS41440A-page 324
APFCON0
BAUDCON
INTCON
PIE1
PIR1
RCSTA
TXREG
TXSTA
Legend:
Note
Name
1:
*
are
— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.
Page provides register information.
PIC16F/LF1825 only.
SYNCHRONOUS SLAVE MODE
EUSART Synchronous Slave
Transmit
RXDTSEL
TMR1GIE
TMR1GIF
ABDOVF
SPEN
CSRC
identical
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
TRANSMISSION
Bit 7
GIE
Transmission”), except in the
SDOSEL
RCIDL
(see
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
(1)
Section 27.4.1.3
SSSEL
TMR0IE
SREN
TXEN
RCIE
RCIF
Bit 5
(1)
EUSART Transmit Data Register
Preliminary
CREN
SCKP
SYNC
Bit 4
INTE
TXIE
TXIF
T1GSEL
SSP1IE
ADDEN
SSP1IF
SENDB
BRG16
IOCIE
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
26.4.2.2
1.
2.
3.
4.
5.
6.
7.
8.
Bit 3
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXREG register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the ANSEL bit for the CK pin (if applicable).
Clear the CREN and SREN bits.
If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start
Significant 8 bits to the TXREG register.
TXCKSEL
TMR0IF
CCP1IE
CCP1IF
BRGH
FERR
transmission
Bit 2
Synchronous Slave Transmission
Set-up:
TMR2IE
TMR2IF
OERR
TRMT
WUE
Bit 1
INTF
 2010 Microchip Technology Inc.
by
writing
TMR1IE
TMR1IF
ABDEN
IOCIF
RX9D
TX9D
Bit 0
the
Register on
Page
301*
Least
125
310
309
308
93
94
98

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