PIC16LF1906T-I/SO Microchip Technology, PIC16LF1906T-I/SO Datasheet
PIC16LF1906T-I/SO
Specifications of PIC16LF1906T-I/SO
Related parts for PIC16LF1906T-I/SO
PIC16LF1906T-I/SO Summary of contents
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... LCD Driver and nanoWatt XLP Technology 2011 Microchip Technology Inc. PIC16LF1904/6/7 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Preliminary Data Sheet DS41569A ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Two Pins • In-Circuit Debug (ICD) via Two Pins • Enhanced Low-Voltage Programming (LVP) • Programmable Code Protection • Power-Saving Sleep mode 2011 Microchip Technology Inc. PIC16LF1904/6/7 Extreme Low-Power Management PIC16LF1904/6/7 with nanoWatt XLP: • Sleep mode 1.8V, typical • Watchdog Timer: 300 nA @ 1.8V, typical • ...
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... PDIP, SOIC, SSOP V /MCLR/RE3 PP SEG12/AN0/RA0 SEG7/AN1/RA1 COM2/AN2/RA2 SEG15/COM3/V +/AN3/RA3 REF SEG4/T0CKI/RA4 SEG5/AN4/RA5 V SEG2/CLKIN/RA7 SEG1/CLKOUT/RA6 T1CKI/T1OSO/RC0 T1OSI/RC1 SEG3/RC2 SEG6/RC3 DS41569A-page Preliminary LCD 116 ( 116 RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCLK/SEG14 RB5/AN13/COM1 RB4/AN11/COM0 RB3/AN9/SEG26/VLCD3 RB2/AN8/SEG25/VLCD2 RB1/AN10/SEG24/VLCD1 RB0/AN12/INT/SEG0 RC7/RX/DT/SEG8 RC6/TX/CK/SEG9 RC5/SEG10 RC4/T1G/SEG11 2011 Microchip Technology Inc. ...
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... FIGURE 2: 28-PIN UQFN PACKAGE DIAGRAM FOR PIC16LF1906 28-Pin UQFN COM2/AN2/RA2 SEG15/COM3/V +/AN3/RA3 REF SEG4/T0CKI/RA4 SEG5/AN4/RA5 V SS SEG2/CLKIN/RA7 SEG1/CLKOUT/RA6 2011 Microchip Technology Inc. PIC16LF1904/6/7 RB3/AN9/SEG26/VLCD3 1 21 RB2/AN8/SEG25/VLCD2 RB1/AN10/SEG24/VLCD1 19 PIC16LF1906 4 RB0/AN12/INT/SEG0 RC7/RX/DT/SEG8 7 15 Preliminary DS41569A-page 5 ...
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... RB7/ICSPDAT/ICDDAT/SEG13 1 40 RB6/ICSPCLK/ICDCLK/SEG14 39 2 RB5/AN13/COM1 3 38 RB4/AN11/COM0 37 4 RB3/AN9/SEG26/VLCD3 5 36 RB2/AN8/SEG25/VLCD2 35 6 RB1/AN10/SEG24/VLCD1 7 34 RB0/AN12/INT/SEG0 RD7/SEG20 30 11 RD6/SEG19 29 12 RD5/SEG18 28 13 RD4/SEG17 14 27 RC7/RX/DT/SEG8 26 15 RC6/TX/CK/SEG9 25 16 RC5/SEG10 24 17 RC4/T1G/SEG11 18 23 RD3/SEG16 22 19 RD2/SEG28 21 20 Preliminary 2011 Microchip Technology Inc. ...
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... FIGURE 4: 44-PIN TQFP (10X10) PACKAGE DIAGRAM FOR PIC16LF1904/7 44-Pin TQFP (10x10) SEG8/DT/RX/RC7 SEG17/RD4 SEG18/RD5 SEG19/RD6 SEG20/RD7 SEG0/INT/AN12/RB0 VLCD1/SEG24/AN10/RB1 VLCD2/SEG25/AN8/RB2 VLCD3/SEG26/AN9/RB3 2011 Microchip Technology Inc. PIC16LF1904/6 PIC16LF1904 Preliminary NC RC0/T1OSO/T1CKI RA6/CLKOUT/SEG1 RA7/CLKIN/SEG2 RE2/AN7/SEG23 RE1/AN6/SEG22 RE0/AN5/SEG21 RA5/AN4/SEG5 RA4/T0CKI/SEG4 DS41569A-page 7 ...
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... PIC16LF1904/6/7 FIGURE 5: 40-PIN UQFN (5X5) PACKAGE DIAGRAM FOR PIC16LF1904/7 40-Pin UQFN (5x5) SEG8/DT/RX/RC7 SEG17/RD4 SEG18/RD5 SEG19/RD6 SEG20/RD7 SEG0/INT/AN12/RB0 VLCD1/SEG24/AN10/RB1 VLCD2/SEG25/AN8/RB2 DS41569A-page PIC16LF1904 Preliminary RC0/T1OSO/T1CKI RA6/CLKOUT/SEG1 RA7/CLKIN/SEG2 RE2/AN7/SEG23 RE1/AN6/SEG22 RE0/AN5/SEG21 RA5/AN4/SEG5 RA4/T0CKI/SEG4 2011 Microchip Technology Inc. ...
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... Note 1: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control. 2: 28-pin only pin location (PIC16LF1906). Location different on 40/44-pin device. 3: 40/44-pin only pin location (PIC16LF1904/1907). Location different on 28-pin device. 2011 Microchip Technology Inc. PIC16LF1904/6/7 17 AN0 — ...
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... Development Support............................................................................................................................................................... 257 25.0 Packaging Information.............................................................................................................................................................. 261 Appendix A: Revision History............................................................................................................................................................. 277 Index .................................................................................................................................................................................................. 279 The Microchip Web Site ..................................................................................................................................................................... 285 Customer Change Notification Service .............................................................................................................................................. 285 Customer Support .............................................................................................................................................................................. 285 Reader Response .............................................................................................................................................................................. 286 Product Identification System............................................................................................................................................................. 287 DS41569A-page 10 ) ................................................................................................................................ 219 ™ Preliminary 2011 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Preliminary DS41569A-page 11 ...
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... PIC16LF1904/6/7 NOTES: DS41569A-page 12 Preliminary 2011 Microchip Technology Inc. ...
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... TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral ADC EUSART Fixed Voltage Reference (FVR) LCD Temperature Indicator Timers Timer0 Timer1 2011 Microchip Technology Inc. PIC16LF1904/6/7 ● ● ● ● ● ● ● ● ● ● ● ● ...
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... Generation CLKIN INTRC Oscillator MCLR LCD See applicable chapters for more information on peripherals. Note 1: DS41569A-page 14 Program Flash Memory CPU Figure 2-1 Timer0 Timer1 ADC Temp. FVR Indicator 10-Bit Preliminary RAM PORTA PORTB PORTC PORTD PORTE EUSART 2011 Microchip Technology Inc. ...
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... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal These pins have interrupt-on-change functionality. Note 1: PIC16LF1906/7 only. 2: 2011 Microchip Technology Inc. PIC16LF1904/6/7 Input Output Type Type TTL CMOS General purpose I/O. AN — ...
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... LCD Analog output. TTL CMOS General purpose I/O. ST — USART asynchronous input. ST CMOS USART synchronous data. — AN LCD Analog output. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2011 Microchip Technology Inc. ...
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... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal These pins have interrupt-on-change functionality. Note 1: PIC16LF1906/7 only. 2: 2011 Microchip Technology Inc. PIC16LF1904/6/7 Input Output Type Type TTL CMOS General purpose I/O. — ...
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... PIC16LF1904/6/7 NOTES: DS41569A-page 18 Preliminary 2011 Microchip Technology Inc. ...
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... Section 3.5 “Indirect Addressing” 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 21.0 “Instruction Set Summary” details. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Saving”, for more details. for more Preliminary DS41569A-page 19 ...
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... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W Reg Timer Brown-out Reset Preliminary RAM Addr 12 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX 2011 Microchip Technology Inc. ...
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... Stack • Indirect Addressing TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16LF1904 PIC16LF1906/7 2011 Microchip Technology Inc. PIC16LF1904/6/7 3.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space. implemented for the PIC16LF1904/6/7 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space ...
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... PROGRAM MEMORY MAP AND STACK FOR PIC16LF1906/7 PC<14:0> 15 Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 1FFFh 2000h Rollover to Page 0 Rollover to Page 3 7FFFh 2011 Microchip Technology Inc. ...
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... FSR require one extra instruction cycle to complete. Example 3-2 demonstrates access- ing the program memory via an FSR. The HIGH directive will set bit<7> label points to a location in program memory. 2011 Microchip Technology Inc. PIC16LF1904/6/7 EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants RETLW DATA0 ...
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... Preliminary Table 3-2. For detailed 3-4. BANKx INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON 2011 Microchip Technology Inc. ...
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... Note 1: second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2011 Microchip Technology Inc. PIC16LF1904/6/7 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register 3-1, contains: as ‘ ...
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... DEVICE MEMORY MAPS The memory maps for PIC16LF1904/6/7 are as shown in Table 3-3. Preliminary BANKED MEMORY PARTITIONING Memory Region Core Registers (12 bytes) Special Function Registers (20 bytes maximum) General Purpose RAM (80 bytes maximum) Common RAM (16 bytes) 2011 Microchip Technology Inc. ...
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TABLE 3-3: PIC16LF1904/6/7 MEMORY MAP BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh PORTB 08Dh TRISB 10Dh 00Eh PORTC 08Eh TRISC 10Eh ...
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TABLE 3-3: PIC16LF1904/6/7 MEMORY MAP (CONTINUED) BANK 8 BANK 9 400h 480h 500h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 40Bh 48Bh 50Bh 40Ch 48Ch 50Ch Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ 46Fh 4EFh ...
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... Unimplemented Read as ‘0’ 7EFh = Unimplemented data memory locations, read as ‘0’. Legend: PIC16LF1904/7 only. Note 1: 2011 Microchip Technology Inc. PIC16LF1904/6/7 BANK 31 F80h Core Registers (Table 3-2) F8Bh F8Ch Unimplemented Read as ‘0’ FE3h STATUS_SHAD ...
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... BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 0000 0000 0000 2011 Microchip Technology Inc. ...
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... Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: Unimplemented, read as ‘1’. 2: PIC16LF1904/7 only. 3: 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit 5 Bit 4 Bit 3 Bit 2 — — RE3 RE2 ...
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... TRMT TX9D 0000 0010 0000 0010 WUE ABDEN 01-0 0-00 01-0 0-00 — — WPUB1 WPUB0 1111 1111 1111 1111 — — — — — — ---- 1--- ---- 1--- — — — — — — 2011 Microchip Technology Inc. ...
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... Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: Unimplemented, read as ‘1’. 2: PIC16LF1904/7 only. 3: 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit 5 Bit 4 Bit 3 Bit 2 IOCBP5 IOCBP4 IOCBP3 IOCBP2 ...
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... Microchip Technology Inc. ...
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... PCL register, all 15 bits of the program counter will change to the values con- tained in the PCLATH register and those being written to the PCL register. 2011 Microchip Technology Inc. PIC16LF1904/6/7 3.3.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL) ...
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... Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will 0x05 return the contents of stack address 0x0F. 0x04 0x03 0x02 0x01 0x00 0x1F 0x0000 STKPTR = 0x1F Preliminary through Figure 3-8 for examples Stack Reset Disabled (STVREN = 0) Stack Reset Enabled (STVREN = 1) 2011 Microchip Technology Inc. ...
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... FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL 2011 Microchip Technology Inc. PIC16LF1904/6/7 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 ...
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... Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will 0x06 Return Address not be overwritten. 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address STKPTR = 0x10 Preliminary 2011 Microchip Technology Inc. ...
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... FIGURE 3-9: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: 2011 Microchip Technology Inc. PIC16LF1904/6/7 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory ...
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... FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2 DS41569A-page 40 Indirect Addressing 0 7 FSRxH Bank Select 11111 Bank 31 Preliminary 7 FSRxL 0 Location Select 2011 Microchip Technology Inc. ...
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... FSRnL Location Select 0x2000 0x29AF 2011 Microchip Technology Inc. PIC16LF1904/6/7 3.5.3 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF ...
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... PIC16LF1904/6/7 NOTES: DS41569A-page 42 Preliminary 2011 Microchip Technology Inc. ...
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... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word 2 is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2011 Microchip Technology Inc. PIC16LF1904/6/7 by device Preliminary DS41569A-page 43 ...
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... ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin DS41569A-page 44 U-1 R/P-1 R/P-1 — CLKOUTEN BOREN<1:0> R/P-1 R/P-1 U-1 WDTE<1:0> — Unimplemented bit, read as ‘1’ Value when blank or after Bulk Erase Preliminary R/P-1 U-1 — bit 8 R/P-1 R/P-1 FOSC<1:0> bit 0 2011 Microchip Technology Inc. ...
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... Flash memory (PIC16LF1907 only Write protection off 10 = 000h to 1FFh write-protected, 200h to 1FFFh may be modified by PMCON control 01 = 000h to FFFh write-protected, 1000h to 1FFFh may be modified by PMCON control 00 = 000h to 1FFFh write-protected, no addresses may be modified by PMCON control 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/P-1 R/P-1 R/P-1 ...
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... See Section 10.4 “User ID, Device ID and Configuration for more information on accessing Word Access” these memory locations. For more information on checksum calculation, “PIC16F193X/LF193X/PIC16F194X/LF194X/PIC16LF 190X Memory Programming (DS41397). DS41569A-page 46 “Write see the Specification” Preliminary 2011 Microchip Technology Inc. ...
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... PIC16LF1904 10 1100 100 PIC16LF1906 10 1100 011 PIC16LF1907 10 1100 010 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision (see Table under DEV<8:0> above). 2011 Microchip Technology Inc. PIC16LF1904/6 DEV<8:3> REV<4:0> Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit DEVICEID< ...
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... PIC16LF1904/6/7 NOTES: DS41569A-page 48 Preliminary 2011 Microchip Technology Inc. ...
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... External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset LPBOR Reset BOR Enable 2011 Microchip Technology Inc. PIC16LF1904/6/7 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. PWRT Zero 72 ms LFINTOSC PWRTEN Preliminary Device Reset DS41569A-page 49 ...
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... V for a DD BOR , the device BORDC Figure 5-2 for more information. Device Operation upon wake- up from Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD 2011 Microchip Technology Inc. ...
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... Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive 2011 Microchip Technology Inc. PIC16LF1904/6/7 (1) T PWRT < T PWRT ...
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... Upon bringing MCLR high, the device will begin Figure 5-3). This is useful for testing purposes or to synchronize more than one device operating in parallel. Preliminary Section 9.0 for more information. Table 5-4 Timer configuration. See for more informa- execution immediately (see 2011 Microchip Technology Inc. ...
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... FIGURE 5-3: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2011 Microchip Technology Inc. PIC16LF1904/6/7 T PWRT T MCLR T OST Preliminary DS41569A-page 53 ...
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... ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition PCON Register 00-1 110x uu-u 0uuu uu-u 0uuu uu-0 uuuu uu-u uuuu 00-1 11u0 uu-u uuuu uu-u u0uu 1u-u uuuu u1-u uuuu 2011 Microchip Technology Inc. ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2011 Microchip Technology Inc. PIC16LF1904/6/7 The PCON register bits are shown in R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q RWDT ...
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... Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets. DS41569A-page 56 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — RWDT RMCLR RI — WDTPS<4:0> Preliminary Register Bit 1 Bit 0 on Page — BORRDY 51 POR BOR SWDTEN 83 2011 Microchip Technology Inc. ...
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... The INTOSC internal oscillator block produces a low and high-frequency clock source, LFINTOSC and HFINTOSC (see Internal Oscillator Block, Figure 6-1). A wide selection of device clock frequencies may be derived from these two clock sources. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Figure 6-1 designated Preliminary DS41569A-page 57 ...
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... HF-500 kHz 1010/ /32 0111 HF-250 kHz 1001/ /64 0110 HF-125 kHz 1000/ /128 0101 HF-62.5 kHz /256 0100 HF-31.25 kHz 0011 /512 0010 LF-31 kHz 0001 0000 Preliminary Low Power Mode Event Switch (SCS<1:0>) 2 Primary Clock 00 01 INTOSC 1x 2011 Microchip Technology Inc. ...
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... Configuration Word 1: • High power, 4-20 MHz (FOSC = 11) • Medium power, 0.5-4 MHz (FOSC = 10) • Low power, 0-0.5 MHz (FOSC = 01) 2011 Microchip Technology Inc. PIC16LF1904/6/7 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...
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... HFINTOSC is running and can be utilized. The High-Frequency Internal Oscillator Status Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value. Preliminary Section 6.3 (High-Frequency Internal (Low-Frequency Internal HFINTOSC Figure 6-1). The frequency derived 2011 Microchip Technology Inc. ...
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... Reset) • 250 kHz • 125 kHz • 62.5 kHz • 31.25 kHz • 31 kHz (LFINTOSC) 2011 Microchip Technology Inc. PIC16LF1904/6/7 Following any Reset, the IRCF<3:0> bits Note: of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz ...
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... System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time HFINTOSC IRCF <3:0> System Clock DS41569A-page 62 Start-up Time 2-cycle Sync 0 2-cycle Sync LFINTOSC turns off unless WDT is enabled 2-cycle Sync 0 Preliminary Running Running Running 2011 Microchip Technology Inc. ...
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... FOSC<1:0> bits in the Configuration Word 1, or from the internal clock source. The OST does not reflect the status of the secondary oscillator. 2011 Microchip Technology Inc. PIC16LF1904/6/7 6.3.3 SECONDARY OSCILLATOR The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral ...
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... Secondary oscillator 00 = Clock determined by FOSC<1:0> in Configuration Word 1. Duplicate frequency derived from HFINTOSC. Note 1: DS41569A-page 64 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary U-0 R/W-0/0 R/W-0/0 SCS<1:0> — bit 0 2011 Microchip Technology Inc. ...
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... CONFIG1 7:0 CP MCLRE — = unimplemented location, read as ‘ 0 ’. Shaded cells are not used by clock sources. Legend: 2011 Microchip Technology Inc. PIC16LF1904/6/7 R-0/q U-0 HFIOFR — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... PIC16LF1904/6/7 NOTES: DS41569A-page 66 Preliminary 2011 Microchip Technology Inc. ...
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... Many peripherals produce Interrupts. Refer to the cor- responding chapters for details. FIGURE 7-1: INTERRUPT LOGIC Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IF) PIR1<0> PIRn<7> PIEn<7> 2011 Microchip Technology Inc. PIC16LF1904/6/7 A block diagram of the interrupt logic is shown in Figure 7.1. TMR0IF TMR0IE INTF INTE ...
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... The latency for synchronous interrupts instruction cycles. For asynchronous interrupts, the latency instruction cycles, depending on when the interrupt occurs. See and Figure 7.3 for more details. Preliminary 2011 Microchip Technology Inc. Figure 7-2 ...
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... Cycle Instruction at PC Interrupt GIE PC-1 PC FSR ADDR PC Execute 3 Cycle Instruction at PC Interrupt GIE PC-1 PC FSR ADDR PC Execute 3 Cycle Instruction at PC 2011 Microchip Technology Inc. PIC16LF1904/6/7 Interrupt Sampled during Q1 PC+1 0004h Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP ...
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... INTF is enabled to be set any time during the Q4-Q1 cycles. DS41569A-page (1) (2) Interrupt Latency Inst ( — Dummy Cycle Dummy Cycle Inst (PC) . Synchronous latency = 3 Section 22.0 “Electrical Preliminary 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) , where T = instruction cycle time Specifications””. 2011 Microchip Technology Inc. ...
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... ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Section 8.0 Preliminary DS41569A-page 71 ...
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... R/W-0/0 R/W-0/0 R/W-0/0 INTE IOCIE TMR0IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary should ensure the R/W-0/0 R-0/0 INTF IOCIF bit 0 2011 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt . 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 U-0 ...
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... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. U-0 U-0 R/W-0/0 — — LCDIE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. U-0 U-0 — — bit 0 ...
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... Unimplemented: Read as ‘0’ bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2011 Microchip Technology Inc. PIC16LF1904/6/7 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
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... U-0 U-0 R/W-0/0 — — LCDIF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. should ensure the U-0 U-0 — — bit 0 ...
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... TMR1GIE ADIE PIE2 — — PIR1 TMR1GIF ADIF PIR2 — — Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF T0CS T0SE PSA ...
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... PIC16LF1904/6/7 NOTES: DS41569A-page 78 Preliminary 2011 Microchip Technology Inc. ...
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... Examples of internal circuitry that might be sourcing current include the FVR module. See 13.0 “Fixed Volt- for more information. age Reference (FVR)” 2011 Microchip Technology Inc. PIC16LF1904/6/7 8.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1 ...
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... LCDIF — WDTPS<4:0> Preliminary 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) Register on Bit 1 Bit 0 Page INTF IOCIF 72 IOCBF1 IOCBF0 118 IOCBN1 IOCBN0 118 IOCBP1 IOCBP0 118 — TMR1IE 73 — — 74 TMR1IF — 75 — — SWDTEN 83 2011 Microchip Technology Inc. ...
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... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2011 Microchip Technology Inc. PIC16LF1904/6/7 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41569A-page 81 ...
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... STATUS register are changed to indicate the event. See Section 3.0 “Memory Organization” WDT STATUS register (Register Mode Active Active Disabled Active Disabled Disabled Preliminary Section 6.0 “Oscillator and 3-1) for more information. WDT Cleared Cleared until the end of OST Unaffected 2011 Microchip Technology Inc. ...
Page 83
... If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. Note 1: 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...
Page 84
... PIC16LF1904/6/7 NOTES: DS41569A-page 84 Preliminary 2011 Microchip Technology Inc. ...
Page 85
... The PMADRH:PMADRL register pair can address maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register. 2011 Microchip Technology Inc. PIC16LF1904/6/7 10.1.1 PMCON1 AND PMCON2 REGISTERS PMCON1 is the control register for Flash program memory accesses ...
Page 86
... Instruction Fetched ignored the next Preliminary FLASH PROGRAM MEMORY READ FLOWCHART Start Read Operation Select (CFGS) Select Word Address (PMADRH:PMADRL) Initiate Read operation ( NOP execution forced NOP execution forced Data read now in PMDATH:PMDATL End Read Operation 2011 Microchip Technology Inc. ...
Page 87
... Ignored MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2011 Microchip Technology Inc. PIC16LF1904/6/7 PMADRH,PMADRL PC+3 INSTR ( PMDATH,PMDATL INSTR ( INSTR( INSTR( instruction ignored instruction ignored Forced NOP Forced NOP ...
Page 88
... FIGURE 10-3: FLASH PROGRAM MEMORY UNLOCK SEQUENCE FLOWCHART Start Unlock Sequence Write 055h to PMCON2 Write 0AAh to PMCON2 Initiate Write or Erase operation ( Instruction Fetched ignored NOP execution forced Instruction Fetched ignored NOP execution forced Unlock Sequence Preliminary 2011 Microchip Technology Inc. End ...
Page 89
... This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. 2011 Microchip Technology Inc. PIC16LF1904/6/7 FIGURE 10-4: FLASH PROGRAM ...
Page 90
... Write AAh ; Set WR bit to begin erase ; NOP instructions are forced as processor starts ; row erase of program memory The processor stalls until the erase process is complete ; after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2011 Microchip Technology Inc. ...
Page 91
... Write opera- tions do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF. 2011 Microchip Technology Inc. PIC16LF1904/6/7 The following steps should be completed to load the write latches and program a row of program memory. ...
Page 92
FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES PMADRH - Row PMADRH<6:0> Address :PMADRL<7:5> Decode ...
Page 93
... Select Program or Config. Memory (CFGS) Select Row Address (PMADRH:PMADRL) Select Write Operation (FREE = 0) Load Write Latches Only (LWLO = 1) 2011 Microchip Technology Inc. PIC16LF1904/6/7 Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Update the word counter (word_cnt--) Yes Last word to ...
Page 94
... NOP instructions are forced as processor writes ; all the program memory write latches simultaneously ; to program memory. ; After NOPs, the processor ; stalls until the self-write process in complete ; after write processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2011 Microchip Technology Inc. ...
Page 95
... Load the starting address of the row to be rewritten. 5. Erase the program memory row. 6. Load the write latches with data from the RAM image. 7. Initiate a programming operation. 2011 Microchip Technology Inc. PIC16LF1904/6/7 FIGURE 10-7: FLASH PROGRAM MEMORY MODIFY FLOWCHART Start Modify Operation Read Operation (Figure x ...
Page 96
... Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location DS41569A-page 96 10-2, the Function Read Access Yes Yes Yes Figure 10-1) Figure 10-1) Preliminary Write Access Yes No No 2011 Microchip Technology Inc. ...
Page 97
... RAM. This image will be used to verify the data currently stored in Flash program memory. Read Operation (Figure x.x) Figure 10-1 PMDAT = No RAM image ? Fail Yes Verify Operation No Last Word ? Yes End Verify Operation 2011 Microchip Technology Inc. PIC16LF1904/6/7 Preliminary DS41569A-page 97 ...
Page 98
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 PMADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0 2011 Microchip Technology Inc. ...
Page 99
... Does not initiate a program Flash read. Unimplemented bit, read as ‘ 1 ’. Note 1: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started ( The LWLO bit is ignored during a program memory erase operation (FREE = 2011 Microchip Technology Inc. PIC16LF1904/6/7 (2) R/W/HC-0/0 R/W/HC-x/q R/W-0/0 FREE ...
Page 100
... PWRTE WDTE<1:0> LVP DEBUG — (1) — VCAPEN — Preliminary W-0/0 W-0/0 W-0/0 bit 0 Register on Bit 1 Bit 0 Page 100 INTF IOCIF 72 Register Bit 10/2 Bit 9/1 Bit 8/0 on Page BOREN<1:0> — 44 FOSC<2:0> BORV STVREN PLLEN 45 — WRT<1:0> 2011 Microchip Technology Inc. ...
Page 101
... Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in 2011 Microchip Technology Inc. PIC16LF1904/6/7 FIGURE 11-1: Write LATx Write PORTx ...
Page 102
... Preliminary 11-2. Table 11-2. PORTA OUTPUT PRIORITY (1) Function Priority SEG12 (LCD) AN0 RA0 SEG7 AN1 RA1 COM2 AN2 RA2 V + REF COM3 SEG15 AN3 RA3 SEG4 T0CKI RA4 SEG5 AN4 RA5 CLKOUT SEG1 RA6 CLKIN SEG2 RA7 2011 Microchip Technology Inc. ...
Page 103
... Bit is cleared bit 7-4 LATA<7:0>: RA<7:4> Output Latch Value bits Writes to PORTA are actually written to the corresponding LATA register. Reads from the PORTA register is Note 1: return of actual I/O pin values. 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-x/x R-x/x R/W-x/x RA4 ...
Page 104
... WDTE<1:0> Preliminary R/W-1/1 R/W-1/1 ANSA1 ANSA0 bit 0 Register Bit 1 Bit 0 on Page ANSA1 ANSA0 104 LATA1 LATA0 103 PS<2:0> 141 RA1 RA0 103 TRISA1 TRISA0 103 Register Bit 9/1 Bit 8/0 on Page BOREN<1:0> — 44 — FOSC<1:0> 2011 Microchip Technology Inc. ...
Page 105
... Note: mode after reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. 2011 Microchip Technology Inc. PIC16LF1904/6/7 11.2.2 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The ...
Page 106
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATB4 LATB3 LATB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RB1 RB0 bit 0 R/W-1/1 R/W-1/1 TRISB1 TRISB0 bit 0 R/W-x/u R/W-x/u LATB1 LATB0 bit 0 2011 Microchip Technology Inc. ...
Page 107
... RB6 TRISB TRISB7 TRISB6 WPUB WPUB7 WPUB6 x = unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. Legend: 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-1/1 R/W-1/1 R/W-1/1 ANSB4 ANSB3 ANSB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) ...
Page 108
... RC7 Priority listed from highest to lowest. Note 1: Preliminary 11-7. Table 11-7. PORTC OUTPUT PRIORITY (1) Function Priority T1OSO T1CKI RC0 T1OSI RC1 SEG2 RC2 SEG6 RC3 SEG11 T1G RC4 SEG10 RC5 SEG9 RC6 TX/CK SEG8 RC7 RX/DT 2011 Microchip Technology Inc. ...
Page 109
... Bit is cleared bit 7-0 LATC<7:0>: PORTC Output Latch Value bits Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is Note 1: return of actual I/O pin values. 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-x/u R/W-x/u R/W-x/u RC4 RC3 RC2 U = Unimplemented bit, read as ‘ ...
Page 110
... Shaded cells are not used by PORTC. Legend: DS41569A-page 110 Bit 5 Bit 4 Bit 3 Bit 2 LATC5 LATC4 LATC3 LATC2 RC5 RC4 RC3 RC2 TRISC5 TRISC4 TRISC3 TRISC2 Preliminary Register Bit 1 Bit 0 on Page LATC1 LATC0 106 RC1 RC0 106 TRISC1 TRISC0 106 2011 Microchip Technology Inc. ...
Page 111
... The user should ensure the bits in the TRISD register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. 2011 Microchip Technology Inc. PIC16LF1904/6/7 11.4.1 PORTD FUNCTIONS AND OUTPUT PRIORITIES Each PORTD pin is multiplexed with other functions ...
Page 112
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATD4 LATD3 LATD2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RD1 RD0 bit 0 R/W-1/1 R/W-1/1 TRISD5 TRISD4 bit 0 R/W-x/u R/W-x/u LATD1 LATD0 bit 0 2011 Microchip Technology Inc. ...
Page 113
... LATD7 LATD6 PORTD RD7 RD6 TRISD TRISD7 TRISD6 x = unknown unchanged unimplemented locations read as ‘ 0 ’. Shaded cells are not used by PORTD. Legend: PIC16LF1904/7 only. Note 1: 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit 5 Bit 4 Bit 3 Bit 2 LATD5 LATD4 LATD3 LATD2 RD5 RD4 ...
Page 114
... Value at POR and BOR/Value at all other Resets (1) (1) U-0 U-1 U-0 — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary U-0 U-0 (1) (1) RE1 RE0 bit 0 U-0 U-0 — — bit 0 2011 Microchip Technology Inc. ...
Page 115
... Analog input. Pin is assigned as analog input When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external Note 1: control of the voltage on the pin. PIC16LF1904/7 only. 2: 2011 Microchip Technology Inc. PIC16LF1904/6/7 U-0 U-0 R/W-x/u (2) LATE2 — ...
Page 116
... WPUE3 — Preliminary U-0 U-0 U-0 — — — bit 0 Register Bit 1 Bit 0 on Page 131 GO/DONE ADON (2) (2) (2) ANSE1 ANSE0 107 (2) LATE1 (2) LATE0 (2) 114 (2) (2) RE1 RE0 114 — — 114 — — 116 2011 Microchip Technology Inc. ...
Page 117
... R RBx IOCBPx 2011 Microchip Technology Inc. PIC16LF1904/6/7 12.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the interrupt-on-change pins of PORTB expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set ...
Page 118
... R/W/HS-0/0 IOCBF4 IOCBF3 IOCBF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware Preliminary R/W-0/0 R/W-0/0 IOCBP1 IOCBP0 bit 0 R/W-0/0 R/W-0/0 IOCBN1 IOCBN0 bit 0 R/W/HS-0/0 R/W/HS-0/0 IOCBF1 IOCBF0 bit 0 2011 Microchip Technology Inc. ...
Page 119
... IOCBF7 IOCBF6 IOCBN IOCBN7 IOCBN6 IOCBP IOCBP7 IOCBP6 TRISB7 TRISB6 TRISB Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ANSB2 TMR0IE INTE IOCIE ...
Page 120
... PIC16LF1904/6/7 NOTES: DS41569A-page 120 Preliminary 2011 Microchip Technology Inc. ...
Page 121
... Conditions HFINTOSC FOSC<2:0> = 100 and IRCF<3:0> = 000x BOREN<1:0> BOR BOREN<1:0> and BORFS = 1 BOREN<1:0> and BORFS = 1 2011 Microchip Technology Inc. PIC16LF1904/6/7 13.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC is routed through two independent amplifiers. Each amplifier can be configured to amplify the reference voltage 2x, to produce the two possible voltage levels ...
Page 122
... Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) (Low Range) (High Range Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG — — Preliminary U-0 R/W-0/0 R/W-0/0 — ADFVR<1:0> bit 0 (2) Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 122 2011 Microchip Technology Inc. ...
Page 123
... The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2011 Microchip Technology Inc. PIC16LF1904/6/7 FIGURE 14-1: 14.2 Minimum Operating V ...
Page 124
... PIC16LF1904/6/7 NOTES: DS41569A-page 124 Preliminary 2011 Microchip Technology Inc. ...
Page 125
... Reserved FVR Buffer1 CHS<4:0> When ADON = 0, all multiplexer inputs are disconnected. Note 1: See ADCON0 register 2: 2011 Microchip Technology Inc. PIC16LF1904/6/7 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) allows ...
Page 126
... Unless using the F Note: system clock frequency will change the ADC adversely affect the ADC result. Section 15.2 Preliminary peri- AD Figure 15-2. specifica- AD for Table 15-1 gives examples of appro- , any changes in the RC clock frequency, which may 2011 Microchip Technology Inc. ...
Page 127
... Sleep mode. FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2011 Microchip Technology Inc. PIC16LF1904/6 DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 16 MHz 8 MHz (2) 125 ns (2) 250 ns (2) (2) 250 ns 500 ns (2) 0.5 s (2) 1.0 ...
Page 128
... ADCON1 register controls the output format. Figure 15-3 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘ 0 ’ LSB bit 0 2011 Microchip Technology Inc. ...
Page 129
... A device Reset forces all registers to their Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2011 Microchip Technology Inc. PIC16LF1904/6/7 15.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 130
... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space 2011 Microchip Technology Inc. ...
Page 131
... ADC is disabled and consumes no operating current See Note 1: Section 13.0 “Fixed Voltage Reference (FVR)” See 2: Section 14.0 “Temperature Indicator Module” 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 132
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets DD (1) + pin REF + pin as the source of the positive reference, be aware that a REF Section 22.0 “Electrical Specifications” Preliminary R/W-0/0 R/W-0/0 ADPREF<1:0> bit 0 for details. 2011 Microchip Technology Inc. ...
Page 133
... Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 134
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES<9:8> bit 0 R/W-x/u R/W-x/u bit 0 2011 Microchip Technology Inc. ...
Page 135
... REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2011 Microchip Technology Inc. PIC16LF1904/6/7 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...
Page 136
... V - REF DS41569A-page 136 V DD Sampling Switch 0. Rss R IC LEAKAGE (1) I 0. Full-Scale Range 0.5 LSB Zero-Scale Full-Scale Transition V REF Transition Preliminary HOLD REF Sampling Switch (k ) Analog Input Voltage 1.5 LSB + 2011 Microchip Technology Inc. ...
Page 137
... TRISA6 TRISB TRISB7 TRISB6 FVRCON FVREN FVRRDY x = unknown unchanged, — = unimplemented read as ‘ 0 ’ value depends on condition. Shaded cells are not Legend: used for ADC module. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit 5 Bit 4 Bit 3 Bit 2 CHS3 CHS2 CHS1 CHS0 ADCS1 ADCS0 — ...
Page 138
... PIC16LF1904/6/7 NOTES: DS41569A-page 138 Preliminary 2011 Microchip Technology Inc. ...
Page 139
... OSC 0 T0CKI 1 TMR0SE TMR0CS 2011 Microchip Technology Inc. PIC16LF1904/6/7 16.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘ ...
Page 140
... Section 22.0 “Electrical Specifications”. 16.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41569A-page 140 Preliminary 2011 Microchip Technology Inc. ...
Page 141
... Timer0 Module Register TRISA TRISA7 TRISA6 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ ...
Page 142
... PIC16LF1904/6/7 NOTES: DS41569A-page 142 Preliminary 2011 Microchip Technology Inc. ...
Page 143
... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2011 Microchip Technology Inc. PIC16LF1904/6/7 • Gate Value Status • Gate Event Interrupt Figure 17 block diagram of the Timer1 module. ...
Page 144
... T1CKI is high then Timer1 is enabled (TMR1ON = 1) when T1CKI is low. T1OSCEN Instruction Clock (F OSC x System Clock (F ) OSC x External Clocking on T1CKI Pin 0 Osc. Circuit on T1OSI/T1OSO Pins 1 LFINTOSC x Preliminary internal clock source is selected, the system clock or they can run Clock Source /4) 2011 Microchip Technology Inc. ...
Page 145
... When switching from synchronous to Note: asynchronous operation possible to skip an increment. When switching from asynchronous to synchronous operation possible to produce an additional increment. 2011 Microchip Technology Inc. PIC16LF1904/6/7 17.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware) ...
Page 146
... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared). Preliminary 2011 Microchip Technology Inc. Figure 17-6 for timing ...
Page 147
... TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2011 Microchip Technology Inc. PIC16LF1904/6/7 17.8 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode ...
Page 148
... PIC16LF1904/6/7 FIGURE 17-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 17-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41569A-page 148 Preliminary 2011 Microchip Technology Inc ...
Page 149
... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2011 Microchip Technology Inc. PIC16LF1904/6/7 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41569A-page 149 ...
Page 150
... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41569A-page 150 Set by hardware on falling edge of T1GVAL Preliminary 2011 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Cleared by software ...
Page 151
... This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 gate flip-flop 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ...
Page 152
... Timer1 gate pin 01 = Timer0 overflow output 10 = Reserved 11 = Reserved DS41569A-page 152 R/W-0/u R/W/HC-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware Preliminary R/W-0/u R/W-0/u T1GSS<1:0> bit 0 2011 Microchip Technology Inc. ...
Page 153
... TRISC7 TRISC6 TMR1CS1 TMR1CS0 T1CON TMR1GE T1GPOL T1GCON Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF ...
Page 154
... PIC16LF1904/6/7 NOTES: DS41569A-page 154 Preliminary 2011 Microchip Technology Inc. ...
Page 155
... SPBRGH SPBRGL BRGH BRG16 2011 Microchip Technology Inc. PIC16LF1904/6/7 The EUSART module includes the following capabilities: • Full-duplex asynchronous transmit and receive • Two-character input buffer • One-character output buffer • Programmable 8-bit or 9-bit character length • Address detection in 9-bit mode • ...
Page 156
... DS41569A-page 156 MSb Data Stop Recovery F OSC ÷ x16 x64 0 0 FERR 0 Register 18-1, Preliminary CREN OERR RCIDL RSR Register LSb • • • ( START RX9 FIFO RX9D RCREG Register 8 Data Bus RCIF Interrupt RCIE 2011 Microchip Technology Inc. ...
Page 157
... I/O function must be disabled by clearing the corresponding ANSEL bit. The TXIF transmitter interrupt flag is set Note: when the TXEN enable bit is set. 2011 Microchip Technology Inc. PIC16LF1904/6/7 18.1.1.2 Transmitting Data A transmission is initiated by writing a character to the TXREG register ...
Page 158
... INTCON register are also set 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. 9. Load 8-bit data into the TXREG register. This will start the transmission. bit 0 bit 1 bit 7/8 Word 1 Preliminary Stop bit 2011 Microchip Technology Inc. ...
Page 159
... SPBRGH TXREG TXSTA CSRC TX9 — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous transmission. Legend: * Page provides register information. PIC16LF1904/7 only. Note 1: 2011 Microchip Technology Inc. PIC16LF1904/6/7 bit 0 bit 1 Word Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 160
... Idle and data bits. The DTRXP bit controls receive data polarity only in Asynchronous mode. In Synchronous mode the DTRXP bit has a different function. Preliminary Receiving Data Section 18.1.2.5 “Receive Framing Section 18.1.2.6 for more Receive Data Polarity 2011 Microchip Technology Inc. ...
Page 161
... The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 2011 Microchip Technology Inc. PIC16LF1904/6/7 18.1.2.7 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When ...
Page 162
... If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 13. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. Preliminary 2011 Microchip Technology Inc. Section 18.3 “EUSART (BRG)”). ...
Page 163
... TXSTA CSRC TX9 — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception. Legend: * Page provides register information. PIC16LF1904/7 only. Note 1: 2011 Microchip Technology Inc. PIC16LF1904/6/7 Start bit 7/8 bit 7/8 Stop Stop bit bit 0 bit ...
Page 164
... Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. R/W-0 R/W-0 (1) SYNC SENDB U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary feature (see Section 18.3.1 R/W-0 R-1 R/W-0 BRGH TRMT TX9D bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 165
... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-0 R/W-0 R-0 CREN ...
Page 166
... Auto-Baud Detect mode is disabled Synchronous mode: Don’t care DS41569A-page 166 R/W-0/0 R/W-0/0 U-0 SCKP BRG16 — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 WUE ABDEN bit 0 2011 Microchip Technology Inc. ...
Page 167
... Don’t care value of SPBRGH, SPBRGL register pair Legend: 2011 Microchip Technology Inc. PIC16LF1904/6/7 If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock ...
Page 168
... EUSART Baud Rate Generator, Low Byte EUSART Baud Rate Generator, High Byte TXEN SYNC SENDB BRGH Preliminary Reset Bit 1 Bit 0 Values on page WUE ABDEN 166 WUE ABDEN 166 OERR RX9D 165 167* 167* TRMT TX9D 164 2011 Microchip Technology Inc. ...
Page 169
... Microchip Technology Inc. PIC16LF1904/6/7 SYNC = 0, BRGH = 0, BRG16 = 18.432 MHz F = 16.000 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) — ...
Page 170
... F = 1.000 MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) 767 300.5 0.16 207 191 1202 0. 2404 0. — — — 21 10417 0. — — — 3 — — — 1 — — — 2011 Microchip Technology Inc. ...
Page 171
... Microchip Technology Inc. PIC16LF1904/6 18.432 MHz F = 16.000 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) 300.0 0.00 15359 300 ...
Page 172
... BRG COUNTER CLOCK RATES BRG Base BRG ABD Clock Clock F /64 F /512 OSC OSC 0 F /16 F /128 OSC OSC 1 F /16 F /128 OSC OSC /32 OSC OSC 1 001Ch Edge #5 Edge #4 bit 5 bit 7 bit 6 Stop bit Auto Cleared 1Ch 00h 2011 Microchip Technology Inc. ...
Page 173
... The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. 2011 Microchip Technology Inc. PIC16LF1904/6/7 18.3.3.1 Special Considerations Break Character ...
Page 174
... This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. 2: DS41569A-page 174 Cleared due to User Read of RCREG Q1Q2 Q3 Q4 Cleared due to User Read of RCREG Sleep Ends Preliminary 2011 Microchip Technology Inc. Auto Cleared Auto Cleared Note 1 ...
Page 175
... Shift Reg. Empty Flag) SENDB Sampled Here SENDB (send Break control bit) 2011 Microchip Technology Inc. PIC16LF1904/6/7 When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. 18.3.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways ...
Page 176
... DTRXP bit of the BAUDCON register. The default state of this bit is ‘0’ which selects high true transmit and receive data. Setting the DTRXP bit to ‘1’ will invert the data resulting in low true transmit and receive data. Preliminary 2011 Microchip Technology Inc. ...
Page 177
... SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit 2011 Microchip Technology Inc. PIC16LF1904/6/7 4. Disable Receive mode by clearing bits SREN and CREN. 5. Enable Transmit mode by setting the TXEN bit 9-bit transmission is desired, set the TX9 bit. ...
Page 178
... SYNC SENDB BRGH Preliminary Register Bit 1 Bit 0 on Page WUE ABDEN 166 WUE ABDEN 166 INTF IOCIF 93 — TMR1IE 94 — TMR1IF 98 OERR RX9D 165 167* 167* TRISC1 TRISC0 134 TRISG1 TRISG0 134 157* TRMT TX9D 164 2011 Microchip Technology Inc. ...
Page 179
... If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. 2011 Microchip Technology Inc. PIC16LF1904/6/7 If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART ...
Page 180
... Preliminary bit 5 bit 6 bit 7 ‘0’ Register Bit 1 Bit 0 on Page — WUE ABDEN 166 — WUE ABDEN 166 INTF IOCIF 93 — — TMR1IE 94 — — TMR1IF 98 160* OERR RX9D 165 167* 167* TRMT TX9D 164 2011 Microchip Technology Inc. ...
Page 181
... Transmission”), except in the “Synchronous Master case of the Sleep mode. 2011 Microchip Technology Inc. PIC16LF1904/6/7 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. The first character will immediately transfer to the TSR register and transmit ...
Page 182
... EUSART Transmit Register TXEN SYNC SENDB BRGH Preliminary Register Bit 1 Bit 0 on Page WUE ABDEN 166 WUE ABDEN 166 INTF IOCIF 93 — TMR1IE 94 — TMR1IF 98 OERR RX9D 165 167* 167* TRISC1 TRISC0 134 157* TRMT TX9D 164 2011 Microchip Technology Inc. ...
Page 183
... CSRC TX9 — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception. Legend: * Page provides register information. 2011 Microchip Technology Inc. PIC16LF1904/6/7 18.4.2.4 Synchronous Slave Reception Set-up: 1. Set the SYNC and SPEN bits and clear the CSRC bit ...
Page 184
... PIC16LF1904/6/7 NOTES: DS41569A-page 184 Preliminary 2011 Microchip Technology Inc. ...
Page 185
... LCD module. COM3 and SEG15 share the same physical pin, therefore SEG15 is not available when using 1/4 multi- 2: plex displays. For the PIC16LF1906 device only. 2011 Microchip Technology Inc. PIC16LF1904/6/7 19.1 LCD Registers The module contains the following registers: • ...
Page 186
... Once the module is configured, the LCDEN bit of the LCDCON register is used to enable or disable the LCD module. The LCD panel can also operate during Sleep by clearing the SLPEN bit of the LCDCON register. DS41569A-page 186 Data 16 (2) ) detailed in Preliminary 2011 Microchip Technology Inc. ...
Page 187
... On these devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 72 segments. Note 1: 2011 Microchip Technology Inc. PIC16LF1904/6/7 U-0 R/W-0/0 R/W-0/0 CS<1:0> — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 188
... DS41569A-page 188 R-0/0 R/W-0/0 R/W-0/0 WA LP<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets C = Only clearable bit Preliminary 2011 Microchip Technology Inc. R/W-1/1 R/W-1/1 bit 0 ...
Page 189
... VLCD1PE: VLCD1 Pin Enable bit 1 = The VLCD1 pin is connected to the internal bias voltage LCDBIAS1 0 = The VLCD1 pin is not connected bit 0 Unimplemented: Read as ‘0’ Normal pin controls of TRISx and ANSELx are unaffected. Note 1: 2011 Microchip Technology Inc. PIC16LF1904/6/7 U-0 R/W-0/0 R/W-0/0 — VLCD3PE VLCD2PE U = Unimplemented bit, read as ‘ ...
Page 190
... Resistor ladder is at maximum resistance (Minimum contrast). DS41569A-page 190 U-0 U-0 R/W-0/0 — — LCDCST<2:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets C = Only clearable bit Preliminary 2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 bit 0 ...
Page 191
... W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SEGx-COMy: Pixel On bits 1 = Pixel on (dark Pixel off (clear) 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-0/0 R/W-0/0 R/W-0/0 SEn SEn SEn U = Unimplemented bit, read as ‘0’ ...
Page 192
... The prescale values are selectable from 1:1 through 1:16. To Ladder Power Control Static ÷4 4-bit Prog ÷ 32 1/2 ÷2 Prescaler Counter 1/3, 1/4 LP<3:0> LMUX<1:0> Preliminary Segment ÷ Clock Ring Counter 2011 Microchip Technology Inc. ...
Page 193
... LCD LCD FIGURE 19-3: LCD BIAS VOLTAGE GENERATION BLOCK DIAGRAM V DD VLCD3PE VLCD3 VLCD2PE VLCD2 VLCD1PE VLCD1 2011 Microchip Technology Inc. PIC16LF1904/6/7 TABLE 19-2: LCD Bias 0 ) LCD Bias 1 LCD and LCD Bias 2 LCD LCD Bias 3 , LCD So that the user is not forced to place external compo- ...
Page 194
... Disabling the internal reference ladder results in all of the ladders being disconnected, allowing external voltages to be supplied. Whenever the LCD module is inactive (LCDA = 0), the internal reference ladder will be turned off. Nominal µA 10 µA 100 µA Preliminary 2011 Microchip Technology Inc. ...
Page 195
... Power Mode Power Mode A COM0 SEG0 COM0-SEG0 2011 Microchip Technology Inc. PIC16LF1904/6/7 The LCDRL register allows switching between two power modes, designated ‘A’ and ‘B’. ‘A’ Power mode is active for a programmable time, beginning at the time when the LCD segments transition. ‘B’ Power mode is the remaining time before the segments or commons change again. The LRLAT< ...
Page 196
FIGURE 19-5: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE A WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE) Single Segment Time 32 kHz Clock Ladder Power ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 Control Segment Clock Segment Data ...
Page 197
FIGURE 19-6: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE B WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE) Single Segment Time 32 kHz Clock Ladder Power ‘H00 ‘H01 ‘H02 ‘H03 ‘H0E ‘H0F Control Segment Clock Segment Data Power Mode ...
Page 198
... Internal LCD Reference Ladder is in ‘A’ Power mode for 7 clocks and ‘B’ Power mode for 25 clocks DS41569A-page 198 R/W-0/0 U-0 R/W-0/0 — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets toFigure 19-4): Figure 19-4): Preliminary R/W-0/0 R/W-0/0 LRLAT<2:0> bit 0 2011 Microchip Technology Inc. ...
Page 199
... Power mode ‘B’, the LCD internal FVR buffer is disabled. The LCD module automatically turns on the Note: Fixed Voltage Reference when needed. 2011 Microchip Technology Inc. PIC16LF1904/6/7 The contrast control circuit is used to decrease the output voltage of the signal source by a total of approximately 10%, when LCDCST = 111. ...
Page 200
... Active 4 61 Active 5 49 Active Preliminary (2) Frame Frequency = (1) /(4 x (LCD Prescaler 1)) (1) /(2 x (LCD Prescaler 2)) (1) /(1 x (LCD Prescaler 3)) (1) /(1 x (LCD Prescaler 4)) /256, T1OSC or LFIN- OSC 19- MHz, TIMER1 @ 1/2 1/3 1/4 122 162 122 81 108 2011 Microchip Technology Inc. ...