PIC24F16KA101-E/MQ Microchip Technology, PIC24F16KA101-E/MQ Datasheet - Page 62

• Manufacturer Part Number: PIC24F16KA101-E/MQ
• Description: 16KB Flash, 1.5KB RAM, 512B EEPROM, 16 MIPS, 18 I/O,16-bit PIC24F Family, NanoWa
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F16KA101-E/MQ

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 16KB (5.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24F16KA102 FAMILY
7.2
The Reset times for various types of device Reset are
summarized in Table 7-3. Note that the system Reset
signal, SYSRST, is released after the POR and PWRT
delay times expire.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
TABLE 7-3:
DS39927B-page 60
POR
BOR
All Others
Note 1:
Note:
Reset Type
(6)
2:
3:
4:
5:
6: If Two-Speed Start-up is enabled, regardless of the Primary Oscillator selected, the device starts with FRC,
Device Reset Times
and in such cases, FRC start-up time is valid.
T
T
T
T
T
oscillator clock to the system.
For detailed operating frequency and timing specifications, see Section 29.0 “Electrical Characteristics”.
OST
POR
PWRT
FRC
LOCK
and T
= Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing
= Power-on Reset delay.
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
= PLL lock time.
= 64 ms nominal if the Power-up Timer is enabled; otherwise, it is zero.
EC
FRC, FRCDIV
LPRC
ECPLL
FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
EC
FRC, FRCDIV
LPRC
ECPLL
FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
LPRC
= RC Oscillator start-up times.
Clock Source
Preliminary
SYSRST Delay
T
T
T
T
T
T
T
POR
POR
POR
POR
POR
POR
POR
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
T
T
T
T
T
T
T
PWRT
PWRT
PWRT
PWRT
PWRT
PWRT
PWRT
+ T
+ T
+ T
+ T
+ T
+ T
+ T
—
PWRT
PWRT
PWRT
PWRT
PWRT
PWRT
PWRT
System Clock
T
T
T
T
© 2009 Microchip Technology Inc.
OST
FRC
FRC
FRC
T
T
T
T
Delay
T
T
T
T
LPRC
LOCK
LPRC
LOCK
+ T
+ T
OST
+ T
OST
+ T
—
FRC
—
FRC
—
LOCK
LOCK
LOCK
LOCK
1, 2
1, 2, 3
1, 2, 3
1, 2, 4
1, 2, 3, 4
1, 2, 5
1, 2, 4, 5
2
2, 3
2, 3
2, 4
2, 3, 4
2, 5
2, 3, 4
Notes
None