PIC24F16KA101-E/MQ Microchip Technology, PIC24F16KA101-E/MQ Datasheet - Page 91

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PIC24F16KA101-E/MQ

Manufacturer Part Number
PIC24F16KA101-E/MQ
Description
16KB Flash, 1.5KB RAM, 512B EEPROM, 16 MIPS, 18 I/O,16-bit PIC24F Family, NanoWa
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet

Specifications of PIC24F16KA101-E/MQ

Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
REGISTER 8-24:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-8
bit 7
bit 6-0
CPUIRQ
R-0
U-0
CPUIRQ: Interrupt Request from Interrupt Controller CPU bit
1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU (this will
0 = No interrupt request is left unacknowledged
Unimplemented: Read as ‘0’
VHOLD: Allows Vector Number Capture and Changes what Interrupt is Stored in VECNUM bit
1 = VECNUM will contain the value of the highest priority pending interrupt, instead of the current
0 = VECNUM will contain the value of the last Acknowledged interrupt (last interrupt that has occurred
Unimplemented: Read as ‘0’
ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
0001 = CPU Interrupt Priority Level is 1
0000 = CPU Interrupt Priority Level is 0
Unimplemented: Read as ‘0’
VECNUM<6:0>: Vector Number of Pending Interrupt bits
0111111 = Interrupt Vector pending is number 135
0000001 = Interrupt Vector pending is number 9
0000000 = Interrupt Vector pending is number 8
happen when the CPU priority is higher than the interrupt priority)
interrupt
with higher priority than the CPU, even if other interrupts are pending)
U-0
R-0
INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
W = Writable bit
‘1’ = Bit is set
VHOLD
R/W-0
R-0
U-0
R-0
Preliminary
PIC24F16KA102 FAMILY
VECNUM<6:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-0
R-0
R-0
R-0
ILR<3:0>
x = Bit is unknown
R-0
R-0
DS39927B-page 89
R-0
R-0
bit 8
bit 0

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