PIC24F16KA101-E/MQ Microchip Technology, PIC24F16KA101-E/MQ Datasheet - Page 92

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PIC24F16KA101-E/MQ

Manufacturer Part Number
PIC24F16KA101-E/MQ
Description
16KB Flash, 1.5KB RAM, 512B EEPROM, 16 MIPS, 18 I/O,16-bit PIC24F Family, NanoWa
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet

Specifications of PIC24F16KA101-E/MQ

Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC24F16KA102 FAMILY
8.4
8.4.1
To configure an interrupt source:
1.
2.
3.
4.
8.4.2
The method that is used to declare an ISR and initialize
the IVT with the correct vector address depends on the
programming language (i.e., C or assembler) and the
language development toolsuite that is used to develop
the application. In general, the user must clear the
interrupt flag in the appropriate IFSx register for the
source of the interrupt that the ISR handles. Otherwise,
the ISR will be re-entered immediately after exiting the
routine. If the ISR is coded in assembly language, it
must be terminated using a RETFIE instruction to
unstack the saved PC value, SRL value and old CPU
priority level.
DS39927B-page 90
Note:
Set the NSTDIS Control bit (INTCON1<15>) if
nested interrupts are not desired.
Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources may be programmed
to the same non-zero value.
Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
Enable the interrupt source by setting the
interrupt enable control bit associated with the
source in the appropriate IECx register.
Interrupt Setup Procedures
INITIALIZATION
INTERRUPT SERVICE ROUTINE
At a device Reset, the IPCx registers are
initialized, such that all user interrupt
sources are assigned to priority level 4.
Preliminary
8.4.3
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
8.4.4
All user interrupts can be disabled using the following
procedure:
1.
2.
To enable user interrupts, the POP instruction may be
used to restore the previous SR value.
Only user interrupts with a priority level of 7 or less can
be disabled. Trap sources (level 8-15) cannot be
disabled.
The DISI instruction provides a convenient way to
disable interrupts of priority levels 1-6 for a fixed period.
Level 7 interrupt sources are not disabled by the DISI
instruction.
Push the current SR value onto the software
stack using the PUSH instruction.
Force the CPU to priority level 7 by inclusive
ORing the value OEh with SRL.
TRAP SERVICE ROUTINE (TSR)
INTERRUPT DISABLE
© 2009 Microchip Technology Inc.

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