PIC24F16KA101-E/SS Microchip Technology, PIC24F16KA101-E/SS Datasheet
PIC24F16KA101-E/SS
Specifications of PIC24F16KA101-E/SS
Related parts for PIC24F16KA101-E/SS
PIC24F16KA101-E/SS Summary of contents
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... XLP™ Technology © 2009 Microchip Technology Inc. PIC24F16KA102 Family 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers Preliminary Data Sheet DS39927B ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Microchip Technology Inc. PIC24F16KA102 FAMILY Analog Features: • 10-Bit 9-Channel Analog-to-Digital Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/ Output Configuration • Charge Time Measurement Unit (CTMU): ...
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... OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6 7 14 U1RTS/SDA1/CN21/RB9 13 8 U1CTS/SCL1/CN22/RB8 9 12 U1TX/INT0/CN23/RB7 /RA5 +/CN2/RA0 REFO/SS1/T2CK/T3CK/CN11/RB15 -/CN3/RA1 3 26 REF AN10/ REF AN11/SDO1/CTPLS/CN13/RB13 5 24 AN12/HLVDIN/CTED2/CN14/RB12 6 23 PGC2/SCK1/CN15/RB11 7 22 PGD2/SDI1/PMD2/CN16/RB10 OC1/C2OUT/INT2/CTED1/CN8/RA6 9 20 IC1/CN9/RA7 10 19 U1RTS/SDA1/CN21/RB9 11 18 U1CTS/SCL1/CN22/RB8 U1TX/INT0/CN23/RB7 PGC3/SCL1 (1) /CN27/RB5 Preliminary /RTCC/OCFA/C1OUT/INT1/CN12/RB14 (1) /CN24/RB6 © 2009 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) (1,2) 20-Pin QFN PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 PGC1/AN3/C1INC/C2INA/U2RX/U2BCLK/CN5/RB1 U1RX/U1BCLK/CN6/RB2 OSCI/CLKI/AN4/C1INB/C2IND/CN30/RA2 OSCO/CLKO/AN5/C1INA/C2INC/CN29/RA3 Note 1: The bottom pad of the QFN package should be connected to Vss. 2: All device pins have a maximum voltage of 3.6V and are not 5V tolerant. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY REFO/SS1/T2CK/T3CK/CN11/RB15 1 15 ...
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... Note 1: Alternative multiplexing for SDA1 and SCL1 when the I2CSEL Configuration bit is set. 2: The bottom pad of the QFN package should be connected to Vss. 3: All device pins have a maximum voltage of 3.6V and are not 5V tolerant. DS39927B-page AN11/SDO1/CTPLS/CN13/RB13 1 21 AN12/HLVDIN/CTED2/CN14/RB12 2 20 PGC2/SCK1/CN15/RB11 3 19 PGD2/SDI1/PMD2/CN16/RB10 PIC24FXXKA102 OC1/C2OUT/INT2/CTED1/CN8/RA6 IC1/CN9/RA7 6 16 U1RTS/SDA1/CN21/RB9 Preliminary © 2009 Microchip Technology Inc. ...
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... Electrical Characteristics .......................................................................................................................................................... 211 30.0 Packaging Information.............................................................................................................................................................. 231 Appendix A: Revision History............................................................................................................................................................. 243 Index .................................................................................................................................................................................................. 245 The Microchip Web Site ..................................................................................................................................................................... 249 Customer Change Notification Service .............................................................................................................................................. 249 Customer Support .............................................................................................................................................................................. 249 Reader Response .............................................................................................................................................................................. 250 Product Identification System ............................................................................................................................................................ 251 © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Preliminary DS39927B-page 5 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39927B-page 6 Preliminary © 2009 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24F08KA101 • PIC24F16KA101 • PIC24F08KA102 • PIC24F16KA102 The PIC24F16KA102 family introduces a new line of extreme low-power Microchip devices: a 16-bit micro- controller family with a broad peripheral feature set and enhanced computational performance. It also offers a ...
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... This information is provided in the pinout diagrams on pages 2, 3 and 4 of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. Preliminary © 2009 Microchip Technology Inc. (8 Kbytes for available on the ...
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... Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire C™ 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Resets (and delays) Instruction Set Packages © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY DC – 32 MHz 8K 16K 2816 5632 1536 512 30 (26/4) PORTA<6:0> PORTB<15:12, 9:7, 4, 2:0> ...
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... Read AGU Write AGU EA MUX 24 16 Inst Latch Inst Register Divide Control Signals Support Reg Array 17x17 Multiplier 16-Bit ALU MCLR 10-Bit Timer2/3 CTMU Timer1 ADC (1) CN1-22 I2C1 OC1/PWM SPI1 Preliminary 16 PORTA (1) RA<0:7> (1) PORTB RB<0:15> Comparators UART1/2 © 2009 Microchip Technology Inc. ...
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... C2OUT CLKI CLKO Schmitt Trigger input buffer, ANA = Analog level input/output, I Legend: Alternative multiplexing when the I2C1SEL Configuration bit is cleared. Note 1: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Input I/O 28-Pin Buffer QFN 27 I ANA A/D Analog Inputs 28 I ANA 1 I ANA ...
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... HLVD Voltage Input Master Clear (device Reset) Input 17 O — Output Compare/PWM Outputs 22 I — Output Compare Fault ANA Main Oscillator Input Connection 7 O ANA Main Oscillator Output Connection 2 2 C™ C/SMBus input buffer Preliminary Description © 2009 Microchip Technology Inc. ...
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... SOSCO SS1 Schmitt Trigger input buffer, ANA = Analog level input/output, I Legend: Alternative multiplexing when the I2C1SEL Configuration bit is cleared. Note 1: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Input I/O 28-Pin Buffer QFN 2 I/O ST In-Circuit Debugger and ICSP™ Programming Clock 1 I/O ...
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... Programming Mode Entry Voltage 28 I ANA A/D and Comparator Reference Voltage (low) Input 27 I ANA A/D and Comparator Reference Voltage (high) Input — Ground Reference for Logic and I/O Pin 2 2 C™ C/SMBus input buffer Preliminary Description © 2009 Microchip Technology Inc. ...
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... REF REF reference for analog modules is implemented The AV and AV pins must always be Note connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY FIGURE 2- MCLR (2) C6 ...
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... V IH Preliminary pin provides two specific device may be all that is required. The DD may be beneficial. A typical ) and fast signal transitions must IL EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC24FXXXX JP C1 and V specifications are met and V specifications are met. IL © 2009 Microchip Technology Inc. ...
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... Refer to Section 28.0 “Electrical Characteristics” for information on V and DDCORE © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible ...
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... Devices” 2.8 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ kΩ resistor to V output to logic low Preliminary on unused pins and drive the SS © 2009 Microchip Technology Inc. ...
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... Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working ...
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... Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register CPU Control Register Preliminary Peripheral Modules © 2009 Microchip Technology Inc. ...
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... PROGRAMMER’S MODEL W0 (WREG) Divider Working Registers W1 W2 Multiplier Registers W10 W11 W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 15 0 Frame Pointer 0 Stack Pointer 0 SPLIM TBLPAG 7 0 PSVPAG 15 0 RCOUNT ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared th low-order bit (for byte-sized data low-order bit of the result has occurred (1,2) Preliminary U-0 U-0 R/W-0, HSC — — DC bit bit Bit is unknown th low-order bit (for word-sized data) © 2009 Microchip Technology Inc. ...
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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — ...
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... All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 3-2. Description Preliminary © 2009 Microchip Technology Inc. ...
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... Device Config Registers Reserved DEVID (2) Memory areas are not displayed to scale. Note: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY The user access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space ...
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... FOSC FWDT FPOR FICD FDS least significant word Instruction Width Preliminary DEVICE CONFIGURATION WORDS FOR PIC24F16KA102 FAMILY DEVICES Configuration Word Addresses F80000 F80004 F80006 F80008 F8000A F8000C F8000E F80010 PC Address (lsw Address) 0 000000h 000002h 000004h 000006h © 2009 Microchip Technology Inc. ...
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... Data RAM 0DFFh 1FFF 7FFFh 8001h FFFFh Data memory areas are not shown to scale. Note: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 4.2.1 DATA SPACE WIDTH The data memory byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all the data space EAs resolve to bytes ...
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... System/DS/HLVD NVM/PMD Preliminary family devices, the entire xx80 xxA0 xxC0 xxE0 Interrupts — — — — — — I/O — — — — — — — — — — — — — — — — — © 2009 Microchip Technology Inc. ...
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TABLE 4-3: CPU CORE REGISTERS MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...
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TABLE 4-4: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name (1) CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 — CN30IE CN29IE — CNPU1 0068 CN15PUE (1) CN14PUE CN13PUE CN12PUE CNPU2 006A — CN30PUE ...
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TABLE 4-6: TIMER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — ...
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TABLE 4-9: I C™ REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — ...
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TABLE 4-12: PORTA REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — ODCA 02C6 — — — — ...
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TABLE 4-15: ADC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...
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TABLE 4-17: REAL-TIME CLOCK AND CALENDAR REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ALRMVAL 0620 ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 RTCVAL 0624 RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC — = unimplemented, read ...
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TABLE 4-20: CLOCK CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR SBOREN — OSCCON 0742 — COSC2 COSC1 COSC0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 OSCTUN 0748 — — — ...
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... W15 (before CALL) PC<22:16> 000000000 <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 4.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...
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... Bits Select 1 PSVPAG 0 8 Bits 23 Bits Preliminary <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx (2) (1) Data EA<14:0> xxx xxxx xxxx xxxx 0 EA 1/0 16 Bits Bits Byte Select © 2009 Microchip Technology Inc. ...
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... D<7:0> of the data address, as above. Note that the data will always be ‘0’ when the upper ‘phantom’ byte is selected (byte select = 1). © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “ ...
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... Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Preliminary Data EA<15:0> 1111’ or © 2009 Microchip Technology Inc. ...
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... When CORCON<2> and EA<15> Program Space PSVPAG The data in the page designated by PSVPAG is mapped into the upper half of the data memory space.... © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Data Space 0 000000h 002BFEh PSV Area 800000h Preliminary 0000h Data EA<14:0> 8000h ...
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... PIC24F16KA102 FAMILY NOTES: DS39927B-page 42 Preliminary © 2009 Microchip Technology Inc. ...
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... Counter Using Table Instruction User/Configuration Space Select © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Real-Time Streaming Protocol (RTSP) is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 32 instructions (96 bytes time, and erase program memory in blocks of 32, 64 and 128 instructions (96,192 and 384 bytes time ...
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... Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the operation is finished. required for Preliminary © 2009 Microchip Technology Inc. ...
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... All other combinations of NVMOP<5:0> are no operation. Note 1: Available in ICSP™ mode only. Refer to device programming specification. 2: The address in the Table Pointer decides which rows will be erased. 3: This bit is used only while accessing data EEPROM. 4: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 U-0 U-0 (4) PGMONLY — ...
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... Initialize PM Page Boundary SFR ; Initialize in-page EA[15:0] pointer ; Set base address of erase block ; Block all interrupts for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary © 2009 Microchip Technology Inc. ...
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... TBLPAG = __builtin_tblpage(&progAddr); offset = &progAddr & 0xFFFF; __builtin_tblwtl(offset, 0x0000); NVMCON = 0x4058; asm("DISI #5"); __builtin_write_NVM(); © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON ...
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... Write PM low word into program latch ; Write PM high byte into program latch // Buffer of data to write // Initialize NVMCON // Initialize PM Page Boundary SFR // Initialize lower word of address // Write to address low word // Write to upper byte // Increment address Preliminary © 2009 Microchip Technology Inc. ...
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... MOV #0x55, W0 MOV W0, NVMKEY MOV #0xAA, W0 MOV W0, NVMKEY BSET NVMCON, #WR © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY ; Block all interrupts for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; 2 NOPs required after setting Wait for the sequence to be completed ...
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... PIC24F16KA102 FAMILY NOTES: DS39927B-page 50 Preliminary © 2009 Microchip Technology Inc. ...
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... W1 “mov W1, NVMKEY // Perform Write/Erase operations asm volatile (“bset NVMCON, #WR “nop “nop © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 6.1 NVMCON Register The NVMCON register (Register 6-1) is also the pri- mary control register for data EEPROM program/erase operations. The upper byte contains the control bits ...
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... Write 1 word DS39927B-page 52 R/W-0 U-0 U-0 PGMONLY — — R/W-0 R/W-0 R/W-0 NVMOP4 NVMOP3 NVMOP2 S = Settable bit ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 NVMOP1 NVMOP0 bit Hardware Clearable bit x = Bit is unknown © 2009 Microchip Technology Inc. ...
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... Erase one, four or eight words • Bulk erase the entire data EEPROM • Write one word • Read one word © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Like program memory operations, the Least Significant bit (LSb) of NVMADR is restricted to even addresses. ...
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... WR bit to initiate the operation and returns control when complete. // Initialize EE Data page pointer // Initizlize lower word of address // Write EEPROM data to write latch // Disable Interrupts For 5 Instructions // Issue Unlock Sequence & Start Write Cycle Preliminary © 2009 Microchip Technology Inc. ...
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... Set up a pointer to the EEPROM location to be erased TBLPAG = __builtin_tblpage(&eeData); offset = __builtin_tbloffset(&eeData); __builtin_tblwtl(offset, newData); asm volatile ("disi #5"); __builtin_write_NVM(); © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 6.4.2 SINGLE-WORD WRITE To write a single word in the data EEPROM, the following sequence must be followed: 1 ...
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... C30 compiler library, is provided in Example 6-5. Program Space Visibility (PSV) can also be used to read locations in the data EEPROM. // Variable located in EEPROM // Initialize EE Data page pointer // Initizlize lower word of address // Write EEPROM data to write latch Preliminary © 2009 Microchip Technology Inc. ...
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... SLEEP Uninitialized W Register © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on Power-on Reset (POR) and unchanged by all other Resets ...
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... R/C-0, HS — — DPSLP R/W-0, HS R/W-0, HS R/W-0, HS (2) WDTO SLEEP IDLE HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 — PMSLP bit 8 R/W-1, HS R/W-1, HS BOR POR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Reset is chosen as shown in Table 7-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 8.0 “Oscillator Configuration” for further details. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY (1) (CONTINUED) Setting Event TABLE 7-2: OSCILLATOR SELECTION vs ...
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... T T POR PWRT FRC POR PWRT POR PWRT OST T PWRT T PWRT T PWRT T PWRT T T PWRT FRC T PWRT T T PWRT FRC — Preliminary © 2009 Microchip Technology Inc. Notes Delay — FRC LPRC LOCK LOCK OST LOCK — FRC LPRC LOCK LOCK ...
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... FDS<DSLPBOR> DSLPBOR will re-arm the POR to ensure the device will reset if V drops below the POR threshold. DD © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 7.5 Brown-out Reset (BOR) The PIC24F16KA102 family devices implement a BOR circuit, which provides the user several configuration and power-saving options. The BOR is controlled by the < ...
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... This mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current. Preliminary © 2009 Microchip Technology Inc. ...
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... PIC24F16KA102 family devices non-maskable traps and unique interrupts; these are summarized in Table 8-1 and Table 8-2. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 8.1.1 ALTERNATE INTERRUPT VECTOR TABLE (AIVT) The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as displayed in Figure 8-1. Access to the ...
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... Note 1: See Table 8-2 for the interrupt vector list. DS39927B-page 64 000000h 000002h 000004h 000014h 00007Ch Interrupt Vector Table (IVT) 00007Eh 000080h 0000FCh 0000FEh 000100h 000102h 000114h Alternate Interrupt Vector Table (AIVT) 00017Ch 00017Eh 000180h 0001FEh 000200h Preliminary © 2009 Microchip Technology Inc. (1) (1) ...
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... Real-Time Clock/Calendar SPI1 Error SPI1 Event Timer1 Timer2 Timer3 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch ...
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... IPL<2:0>, also indicates the current CPU priority level. IPL3 is a read-only bit so that the trap events cannot be masked by the user’s software. All interrupt registers are described in Register 8-1 through Register 8-21, in the following sections. Preliminary © 2009 Microchip Technology Inc. ...
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... The value in parentheses indicates the interrupt priority level if IPL3 = 1. The IPL Status bits are read-only when NSTDIS (INTCON1<15> Bit 8 and bits 4 through 0 are described in Section 3.0 “CPU”. Note: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — — ...
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... U-0 R/C-0, HSC R/W-0 (2) (1) — IPL3 PSV HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown ...
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... Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — — ...
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... Interrupt on positive edge DS39927B-page 70 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — INT2EP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1EP INT0EP bit Bit is unknown ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0, HS R/W-0, HS R/W-0, HS U1TXIF U1RXIF ...
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... Interrupt request has not occurred DS39927B-page 72 U-0 U-0 U-0 — — — R/W-0, HS R/W-0, HS R/W-0, HS INT1IF CNIF CMIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock and Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — — ...
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... Unimplemented: Read as ‘0’ DS39927B-page 74 U-0 U-0 U-0 — — — U-0 R/W-0, HS R/W-0, HS — CRCIF U2ERIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 R/W-0, HS — HLVDIF bit 8 R/W-0, HS U-0 U1ERIF — bit Bit is unknown ...
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... IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE ...
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... Interrupt request not enabled DS39927B-page 76 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 INT1IE CNIE CMIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock and Calendar Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... Unimplemented: Read as ‘0’ DS39927B-page 78 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — CRCIE U2ERIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 R/W-0 — HLVDIE bit 8 R/W-0 U-0 U1ERIE — bit Bit is unknown ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 ...
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... Unimplemented: Read as ‘0’ DS39927B-page 80 R/W-0 U-0 U-0 T2IP0 — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 ...
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... Interrupt source is disabled DS39927B-page 82 R/W-0 U-0 U-0 NVMIP0 — — R/W-0 U-0 R/W-1 AD1IP0 — U1TXIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 U1TXIP1 U1TXIP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 85
... Unimplemented: Read as ‘0’ bit 2-0 SI2C1P<2:0>: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 ...
Page 86
... Interrupt source is disabled DS39927B-page 84 U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — — INT1IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1IP1 INT1IP0 bit Bit is unknown ...
Page 87
... INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 ...
Page 88
... Unimplemented: Read as ‘0’ DS39927B-page 86 U-0 U-0 R/W-1 — — RTCIP2 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/W-0 R/W-0 RTCIP1 RTCIP0 bit 8 U-0 U-0 — — bit Bit is unknown ...
Page 89
... U1ERIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 ...
Page 90
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 HLVDIP1 HLVDIP0 bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 91
... VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM< ...
Page 92
... Only user interrupts with a priority level less can be disabled. Trap sources (level 8-15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period. Level 7 interrupt sources are not disabled by the DISI instruction. Preliminary © 2009 Microchip Technology Inc. ...
Page 93
... Secondary Oscillator SOSCO SOSCEN Enable SOSCI Oscillator © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY • Software-controllable switching between various clock sources. • Software-controllable postscaler for selective clocking of CPU for system power savings. • System frequency range declaration bits for EC mode ...
Page 94
... FCKSM<1:0> are both programmed (‘00’). Oscillator Source POSCMD<1:0> Internal 11 Internal 11 Internal 11 Secondary 00 Primary 10 Primary 00 Primary 10 Primary 01 Primary 00 Internal 11 Internal 11 Preliminary bit settings. The oscillator bits, POSCMD<1:0> FNOSC<2:0> Note 1, 2 111 1 110 1 101 1 100 011 011 010 010 010 1 001 1 000 © 2009 Microchip Technology Inc. ...
Page 95
... Reset values for these bits are determined by the FNOSC Configuration bits. Note 1: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 2: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY The Clock Divider register (Register 9-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator ...
Page 96
... Initiate an oscillator switch to clock source specified by NOSC<2:0> bits 0 = Oscillator switch is complete Reset values for these bits are determined by the FNOSC Configuration bits. Note 1: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 2: DS39927B-page 94 (2) Preliminary © 2009 Microchip Technology Inc. ...
Page 97
... Unimplemented: Read as ‘0’ This bit is automatically cleared when the ROI bit is set and an interrupt occurs. Note 1: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-1 R/W-0 R/W-0 (1) DOZE0 ...
Page 98
... U-0 U-0 — — R/W-0 R/W-0 (1) (1) (1) TUN4 TUN3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 (1) (1) (1) TUN2 TUN1 TUN0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 99
... Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits ...
Page 100
... OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches. Preliminary /2) available in OSC drive external devices in the © 2009 Microchip Technology Inc. ...
Page 101
... Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’ The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Note 1: Sleep mode. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 R/W-0 R/W-0 ROSEL RODIV3 ...
Page 102
... PIC24F16KA102 FAMILY NOTES: DS39927B-page 100 Preliminary © 2009 Microchip Technology Inc. ...
Page 103
... BSET DSCON, #DSEN ; Enable Deep Sleep PWRSAV #SLEEP_MODE ; Put the device into Deep SLEEP mode © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY The assembly syntax of the PWRSAV instruction is shown in Example 10-1. SLEEP_MODE and IDLE_MODE are con- Note: stants defined in the assembler include file for the selected device ...
Page 104
... Deep Sleep mode. Exiting from Deep Sleep mode requires a change on the INT0 pin while in Deep Sleep mode. Preliminary © 2009 Microchip Technology Inc. within one CY supply POR circuit, the ...
Page 105
... Deep Sleep mode. After exiting Deep Sleep, software can restore the data by reading the registers and clearing the RELEASE bit (DSCON<0>). © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 10.2.4.4 I/O Pins During Deep Sleep ...
Page 106
... The DSEN bit is automatically cleared. 12. Read and clear the DPSLP status bit in RCON, and the DSWAKE status bits. 13. Read the DSGPRx registers (optional). 14. Once all state related configurations are complete, clear the RELEASE bit. 15. Application resumes normal operation. Preliminary ) PORs © 2009 Microchip Technology Inc. ...
Page 107
... All register bits are reset only in the case of a POR event outside of Deep Sleep mode. Note 1: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this 2: re-arms POR. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY (1) U-0 U-0 U-0 — ...
Page 108
... U-0 U-0 U-0 — — — R/W-0, HS R/W-0, HS R/W-0, HS DSWDT DSRTCC DSMCLR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2,3) Preliminary (1) U-0 R/W-0, HS — DSINT0 bit 8 U-0 R/W-0, HS (2,3) — DSPOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 109
... CPU Idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by set- ting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 10.4 Selective Peripheral Module Control ...
Page 110
... PIC24F16KA102 FAMILY NOTES: DS39927B-page 108 Preliminary © 2009 Microchip Technology Inc. ...
Page 111
... CK WR PORT Data Latch Read LAT Read PORT © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...
Page 112
... Make sure that there is no external pull-up source/pull-down sink when the internal pull-ups/pull-downs are enabled. Pull-ups and pull-downs on change Note: notification disabled configured as a digital output. Preliminary , enable DD , enable pins should always be whenever the port pin is © 2009 Microchip Technology Inc. ...
Page 113
... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Figure 12-1 presents a block diagram of the 16-bit Timer1 module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS<1:0> bits. ...
Page 114
... DS39927B-page 112 U-0 U-0 — — R/W-0 U-0 R/W-0 TCKPS0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 115
... Timer2 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 interrupt flags. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY To configure Timer2/3 for 32-bit operation: 1. Set the T32 bit (T2CON<3> = 1). ...
Page 116
... The 32-Bit Timer Configuration (T32) bit must be set for 32-bit timer/counter operation. All control bits Note 1: are respective to the T2CON register. DS39927B-page 114 1x Gate Sync PR3 PR2 Comparator LSB TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2009 Microchip Technology Inc. ...
Page 117
... TIMER2 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal FIGURE 13-3: TIMER3 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T3CK TGATE 1 Set T3IF 0 Reset ADC Event Trigger Equal © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 1x Gate Sync TMR2 Sync Comparator PR2 Sync ...
Page 118
... DS39927B-page 116 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) /2) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 119
... External clock from the T3CK pin (on the rising edge Internal clock (F OSC bit 0 Unimplemented: Read as ‘0’ When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer Note 1: functions are set through T2CON. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 (1) — — R/W-0 ...
Page 120
... PIC24F16KA102 FAMILY NOTES: DS39927B-page 118 Preliminary © 2009 Microchip Technology Inc. ...
Page 121
... Mode Select ICOV, ICBNE (IC1CON<4:3>) IC1CON System Bus © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY The PIC24F16KA102 family devices have one input capture channel. The input capture module has multiple operating modes, which are selected via the IC1CON register. The operating modes include: • ...
Page 122
... DS39927B-page 120 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE ICM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM1 ICM0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 123
... OC1IE bit. For further information on peripheral interrupts, refer to Section 8.0 “Interrupt Controller”. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 10. To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to ‘ ...
Page 124
... Table 15-1 provides an example of PWM frequencies and resolutions for a device operating at 10 MIPS log 10 F • (Timer Prescale Value) PWM log ( /2, Doze mode and PLL are disabled. CY OSC Preliminary CALCULATING THE PWM (1) PERIOD • (Timer Prescale Value Doze mode CY OSC (1) ) bits © 2009 Microchip Technology Inc. ...
Page 125
... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (F PWM Frequency 30.5 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 Based /2, Doze mode and PLL are disabled. Note 1: CY OSC © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY )/log 2) bits 10 2) bits 61 Hz 122 Hz 977 FFFFh 7FFFh 0FFFh ...
Page 126
... Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the 3: time bases associated with the module. DS39927B-page 124 Set Flag bit OC1IF Output Logic 3 OCM<2:0> Mode Select OCTSEL 0 1 Period Match Signals (3) (3) from Time Bases Preliminary ( (1) OC1 R Output Enable (2) OCFA © 2009 Microchip Technology Inc. ...
Page 127
... Initialize OC1 pin high, compare event forces OC1 pin low 001 = Initialize OC1 pin low, compare event forces OC1 pin high 000 = Output compare channel is disabled OCFA pin controls OC1 channel. Note 1: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — ...
Page 128
... R/W-0 R/W-0 R/W-0 (3) SMBUSDEL OC1TRIS RTSECSEL1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C™)”. Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 (1,4) (1,4) RTSECSEL0 — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 129
... SDO1 and SS1 are not used. Block diagrams of the module in Standard and Enhanced Buffer modes are displayed in Figure 16-1 and Figure 16-2. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY The devices of the PIC24F16KA102 family offer one SPI module on a device. ...
Page 130
... Control Clock SDO1 bit 0 SDI1 SPI1SR Transfer SPI1BUF Read SPI1BUF DS39927B-page 128 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer Write SPI1BUF 16 Internal Data Bus Preliminary 1:1/4/16/64 Primary F CY Prescaler SPI1CON1<1:0> SPI1CON1<4:2> Enable Master Clock © 2009 Microchip Technology Inc. ...
Page 131
... SDO1 bit 0 SDI1 SPI1SR Transfer 8-Level FIFO Receive Buffer SPI1BUF Read SPI1BUF © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPI1BUF register using interrupts: a) Clear the respective SPI1IF bit in the IFS0 register ...
Page 132
... R/W-0 SISEL2 SISEL1 SISEL0 HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-0, HSC R-0, HSC SPIBEC1 SPIBEC0 bit 8 R-0, HSC R-0, HSC SPITBF SPIRBF bit Clearable bit x = Bit is unknown © 2009 Microchip Technology Inc. ...
Page 133
... Automatically cleared in hardware when core reads SPI1BUF location, reading SPI1RXB. In Enhanced Buffer mode: Automatically set in hardware when SPI1 transfers data from SPI1SR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPI1SR. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Preliminary DS39927B-page 131 ...
Page 134
... DS39927B-page 132 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE2 SPRE1 SPRE0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 PPRE1 PPRE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 135
... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — — ...
Page 136
... Preliminary (1) 4:1 6:1 8:1 4000 2667 2000 1000 667 500 250 167 125 1250 833 625 313 208 156 © 2009 Microchip Technology Inc. ...
Page 137
... SCL1 and SDA1 during device configuration. Pin assignment is controlled by the I2C1SEL Configuration bit. Programming this bit (= 0) multiplexes the module to the SCL1 and SDA1 pins. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 17.2 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
Page 138
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2C1TRN LSB Reload Control Preliminary Internal Data Bus Read Write I2C1MSK Read Write Read Write I2C1STAT Read Write I2C1CON Read Write Read Write I2C1BRG Read © 2009 Microchip Technology Inc. ...
Page 139
... Note 1: Address will be Acknowledged only if GCEN = 1. 2: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. 3: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 17.4 Slave Address Masking The I2C1MSK register (Register 17-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes ...
Page 140
... ACKEN RCEN PEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C™ pins are controlled by port functions 2 C slave slave slave) Preliminary R/W-0 R/W-0 DISSLW SMEN bit 8 R/W-0, HC R/W-0, HC RSEN SEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 141
... Repeated Start condition not in progress bit 0 SEN: Start Condition Enable bit (when operating Initiates Start condition on SDA1 and SCL1 pins; hardware clear at end of master Start sequence 0 = Start condition not in progress © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 2 C master; applicable during master receive) 2 ...
Page 142
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared nd byte of matched 10-bit address; hardware clear at Stop detection slave) Preliminary R-0, HSC R-0, HSC GCSTAT ADD10 bit 8 R-0, HSC R-0, HSC RBF TBF bit Bit is unknown 2 C module is busy © 2009 Microchip Technology Inc. ...
Page 143
... Hardware set when I2C1RCV is written with received byte; hardware clear when software reads I2C1RCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2C1TRN is full 0 = Transmit complete, I2C1TRN is empty Hardware set when software writes to I2C1TRN; hardware clear at completion of data transmission. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 2 C slave device address byte. ...
Page 144
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-0 R/W-0 — AMSK9 AMSK8 bit 8 R/W-0 R/W-0 R/W-0 AMSK1 AMSK0 bit Bit is unknown U-0 U-0 — — bit 8 R/W-0 U-0 (1,3) (1,3) RTSECSEL0 — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 145
... UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA Hardware Flow Control UARTx Receiver UARTx Transmitter © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY • Fully Integrated Baud Rate Generator (IBRG) with 16-Bit Prescaler • Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS • ...
Page 146
... BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. Preliminary /(16 * 65536). UART BAUD RATE WITH (1) BRGH = • (UxBRG + – • Baud Rate = F /2, Doze mode CY OSC /4 CY (1) © 2009 Microchip Technology Inc. ...
Page 147
... Write ‘55h’ to UxTXREG – loads the Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 18.5 Receiving in 8-Bit or 9-Bit Data Mode 1. ...
Page 148
... IREN RTSMD — R/W-0 R/W-0 R/W-0 RXINV BRGH PDSEL1 HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary (2) (2) R/W-0 R/W-0 UEN1 UEN0 bit 8 R/W-0 R/W-0 PDSEL0 STSEL bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 149
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit This feature is only available for the 16x BRG mode (BRGH = 0). Note 1: Bit availability depends on pin availability. 2: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Preliminary DS39927B-page 147 ...
Page 150
... R-0, HSC RIDLE PERR FERR HC = Hardware Clearable bit HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-0, HSC R-1, HSC UTXBF TRMT bit 8 R/C-0, HS R-0, HSC OERR URXDA bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 151
... Receive buffer has not overflowed (clearing a previously set OERR bit (1 → 0 transition) will reset the receiver buffer and the RSR to the empty state) bit 0 URXDA: Receive Buffer Data Available bit (read-only Receive buffer has data; at least one more character can be read 0 = Receive buffer is empty © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Preliminary DS39927B-page 149 ...
Page 152
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-x W-x — UTX8 bit 8 W-x W-x UTX1 UTX0 bit Bit is unknown U-0 R-0, HSC — URX8 bit 8 R-0, HSC R-0, HSC URX1 URX0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 153
... Alarm Event Comparator Alarm Registers with Masks Repeat Counter © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY • Alarm-configurable for half a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month or one year • Alarm repeat with decrementing counter • ...
Page 154
... Secondary Oscillator (SOSC) is used as the reference clock and when the bit is ‘0’, LPRC is used as the reference clock. Preliminary ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMVAL<15:8> ALRMVAL<7:0> ALRMMIN ALRMSEC ALRMWD ALRMHR ALRMMNTH ALRMDAY — — © 2009 Microchip Technology Inc. ...
Page 155
... The RCFGCAL register is only affected by a POR. Note 1: A write to the RTCEN bit is only allowed when RTCWREN = 1. 2: This bit is read-only cleared to ‘0’ write to the lower half of the MINSEC register. 3: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R-0, HSC R-0, HSC R/W-0 (3) ...
Page 156
... R/W-0 R/W-0 R/W-0 SMBUSDEL OC1TRIS RTSECSEL1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary (1) (CONTINUED) U-0 U-0 — — bit 8 R/W-0 U-0 (1) (1) RTSECSEL0 — bit Bit is unknown 2 C™)”. © 2009 Microchip Technology Inc. ...
Page 157
... ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times . . . 00000000 = Alarm will not repeat The counter decrements on any alarm event prevented from rolling over from 00h to FFh unless CHIME = 1. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 R/W-0 R/W-0 AMASK2 AMASK1 AMASK0 ...
Page 158
... DAYONE3 DAYONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-x R/W-x YRONE1 YRONE0 bit Bit is unknown R/W-x R/W-x MTHONE1 MTHONE0 bit 8 R/W-x R/W-x DAYONE1 DAYONE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 159
... SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 R/W-x — ...
Page 160
... HRONE3 HRONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-x R/W-x MTHONE1 MTHONE0 bit 8 R/W-x R/W-x DAYONE1 DAYONE0 bit Bit is unknown (1) R/W-x R/W-x WDAY1 WDAY0 bit 8 R/W-x R/W-x HRONE1 HRONE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 161
... SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-x R/W-x R/W-x MINTEN0 ...
Page 162
... To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0 recommended that the ALCFGRPT register and CHIME bit be changed when RTCSYNC = 0. Preliminary © 2009 Microchip Technology Inc. ...
Page 163
... Every minute 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week 1000 - Every month (1) 1001 - Every year Annually, except when configured for February 29. Note 1: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Day of the Week Month Day Hours h h ...
Page 164
... PIC24F16KA102 FAMILY NOTES: DS39927B-page 162 Preliminary © 2009 Microchip Technology Inc. ...
Page 165
... OUT IN BIT 0 D OUT 1 clk © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY The programmable CRC generator offers the following features: • User-programmable polynomial CRC equation • Interrupt output • Data FIFO The module implements a software-configurable CRC generator. The terms of the polynomial and its length can be programmed using the CRCXOR (X< ...
Page 166
... CSIDL bit must be cleared prior to entry into the mode. If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available. Preliminary © 2009 Microchip Technology Inc BIT 15 clk ...
Page 167
... CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter turned off bit 3-0 PLEN<3:0>: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R-0, HSC R-0, HSC R-0, HSC VWORD4 ...
Page 168
... Unimplemented: Read as ‘0’ DS39927B-page 166 R/W-0 R/W-0 R/W-0 X12 X11 X10 R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared n Enable bits Preliminary R/W-0 R/W bit 8 R/W-0 U-0 X1 — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 169
... Trip Point V DD HLVDIN HLVDEN © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt ...
Page 170
... DS39927B-page 168 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — HLVDL3 HLVDL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 HLVDL1 HLVDL0 bit Bit is unknown ...
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... V REF voltage reference inputs may be shared with other analog input pins. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY A block diagram of the A/D Converter is displayed in Figure 22-1. To perform an A/D conversion: 1. ...
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... S/H DAC V INL 10-Bit SAR Data Formatting ADC1BUF0: ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS INH AD1PCFG AD1CSSL INL Sample Control Control Logic Input MUX Control Pin Config Control Preliminary Internal Data Bus 16 Comparator + Conversion Logic Conversion Control © 2009 Microchip Technology Inc. ...
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... A/D conversion is done 0 = A/D conversion is not done Values of ADC1BUFn registers will not retain their values once the ADON bit is cleared. Read out the Note 1: conversion values from the buffer before disabling the module. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY U-0 U-0 U-0 — ...
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... REF AV External V DD External V + pin External V REF (1) th sample/convert sequence th sample/convert sequence nd sample/convert sequence . This sets the inputs of the A Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 BUFM ALTS bit Bit is unknown - pin REF - pin REF SS © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 5-0 ADCS<5:0>: A/D Conversion Clock Select bits 11111 = 64 • 11110 = 63 • · · · 00001 = 3 • 00000 = 2 • © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 R/W-0 R/W-0 SAMC4 SAMC3 SAMC2 R/W-0 R/W-0 R/W-0 ADCS4 ADCS3 ADCS2 U = Unimplemented bit, read as ‘ ...
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... U-0 R/W-0 R/W-0 — CH0SB3 CH0SB2 R/W-0 R/W-0 R/W-0 CH0SA4 CH0SA3 CH0SA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared - Preliminary R/W-0 R/W-0 CH0SB1 CH0SB0 bit 8 R/W-0 R/W-0 CH0SA1 CH0SA0 bit Bit is unknown /2) BG /2) BG © 2009 Microchip Technology Inc. ...
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... Analog channel omitted from input scan bit 9-6 Unimplemented: Read as ‘0’ bit 5-0 CSSL<5:0>: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 R/W-0 R/W-0 PCFG12 PCFG11 ...
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... Threshold Voltage Leakage Current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch Resistance Sample/Hold Capacitance (from DAC) HOLD Preliminary ≤ 5 kΩ (Typical HOLD = DAC capacitance = 4.4 pF (Typical negligible if Rs ≤ 5 kΩ. PIN © 2009 Microchip Technology Inc. ...
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... Voltage Level © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Preliminary DS39927B-page 177 ...
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... PIC24F16KA102 FAMILY NOTES: DS39927B-page 178 Preliminary © 2009 Microchip Technology Inc. ...
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... BG C INA X CV REF © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. A simplified block diagram of the module is displayed in Figure 23-1 ...
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... COE V C INC REF CxOUT Pin Comparator V > CON = 1 , CREF = 1 COE REF CxOUT Pin Preliminary Pin , CCH<1:0> COE - CxOUT Pin , CCH<1:0> COE - - Cx + CxOUT Pin Compare REF , CCH<1:0> COE - CxOUT Pin Compare REF , CCH<1:0> COE - CxOUT Pin © 2009 Microchip Technology Inc. ...
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... CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects Inverting input of comparator connects to CxIND pin 01 = Inverting input of comparator connects to CxINC pin 00 = Inverting input of comparator connects to CxINB pin © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 U-0 U-0 CLPWR — ...
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... U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R-0, HSC R-0, HSC C2EVT C1EVT bit 8 R-0, HSC R-0, HSC C2OUT C1OUT bit Bit is unknown ...
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... REF AV DD CVRSS = 0 CVREN CVRR V - REF © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 24.1 Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register (Register 24-1). The comparator voltage reference provides two ranges of comprehensive output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON< ...
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... DD SS Value Selection 0 ≤ CVR<3:0> ≤ 15 bits REF ) RSRC ) RSRC )) + V - RSRC REF ) + (CVR<3:0>/32 RSRC REF Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 CVR2 CVR1 CVR0 bit Bit is unknown /24 step size /32 step size - © 2009 Microchip Technology Inc. ...
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... CTMUICON register selects the current range of current source and trims the current. FIGURE 25-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT C APP © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 25.1 Measuring Capacitance The CTMU generating an output pulse with a width equal to the time between edge events on two separate input channels ...
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... EDG1 Current Source EDG2 Output Pulse A/D Converter ANx PIC24F Device CTMU EDG1 Current Source Comparator - C2 CV REF Preliminary ) is connected to DELAY , is connected to C2INA. REF when an edge event DELAY charges above the CV DELAY REF and DELAY CTPLS © 2009 Microchip Technology Inc. ...
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... EDG2SEL<1:0>: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/W-0 R/W-0 R/W-0 TGEN EDGEN EDGSEQEN R/W-0 ...
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... DS39927B-page 188 R/W-0 R/W-0 R/W-0 ITRIM2 ITRIM1 ITRIM0 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 IRNG1 IRNG0 bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... BWRP: Boot Segment Program Flash Write Protection bit 1 = Boot segment may be written 0 = Boot segment is write-protected This selection should not be used in PIC24F08KA1XX devices. Note 1: © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 26.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘ ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 R/P-1 — — FNOSC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/C-1 R/C-1 GSS0 GWRP bit Bit is unknown R/P-1 R/P-1 FNOSC1 FNOSC0 ...
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... CLKO output disabled bit 1-0 POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator disabled oscillator mode selected oscillator mode selected 00 = External clock mode selected © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/P-1 R/P-1 R/P Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 194
... DS39927B-page 192 R/P-1 R/P-1 R/P-1 FWPSA WDTPS3 WDTPS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/P-1 R/P-1 WDTPS1 WDTPS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... FICD<1:0:> ICD Pin Select bits 11 = PGC1/PGD1 are used for programming and debugging the device 10 = PGC2/PGD2 are used for programming and debugging the device 01 = PGC3/PGD3 are used for programming and debugging the device 00 = Reserved; do not use © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY R/P-1 R/P-1 (3) ...
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... DS39927B-page 194 R/P-1 R/P-1 R/P Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/P-1 R/P-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 15-8 FAMID<7:0>: Device Family Identifier bits 00001011 = PIC24F16KA102 family bit 7-0 DEV<7:0>: Individual Device Identifier bits 00000011 = PIC24F16KA102 00001010 = PIC24F08KA102 00000001 = PIC24F16KA101 00001000 = PIC24F08KA101 REGISTER 26-10: DEVREV: DEVICE REVISION REGISTER U-0 U-0 U-0 — — — ...
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... WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. LPRC Control WDTPS<3:0> WDT Postscaler Counter 1:1 to 1:32.768 1 ms/4 ms Preliminary Wake from Sleep WDT Overflow Reset © 2009 Microchip Technology Inc. ...
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... GWRP, for the general segment in the Configuration Word. When these bits are programmed to ‘0’, internal write and erase operations to program memory are blocked. © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 26.5 In-Circuit Serial Programming PIC24F16KA102 family microcontrollers can be serially programmed while in the end application circuit ...
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... PIC24F16KA102 FAMILY NOTES: DS39927B-page 198 Preliminary © 2009 Microchip Technology Inc. ...