PIC24F16KA101T-I/MQ Microchip Technology, PIC24F16KA101T-I/MQ Datasheet - Page 53

16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 16 I/O,16-bit PIC24F Family, NanoWatt

PIC24F16KA101T-I/MQ

Manufacturer Part Number
PIC24F16KA101T-I/MQ
Description
16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 16 I/O,16-bit PIC24F Family, NanoWatt
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr

Specifications of PIC24F16KA101T-I/MQ

Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24F16KA101T-I/MQ
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
6.0
The data EEPROM memory is a Nonvolatile Memory
(NVM), separate from the program and volatile data
RAM. Data EEPROM memory is based on the same
Flash technology as program memory, and is optimized
for both long retention and a higher number of
erase/write cycles.
The data EEPROM is mapped to the top of the user
program memory space, with the top address at
program memory address, 7FFE00h to 7FFFFFh. The
size of the data EEPROM is 256 words in
PIC24F16KA102 devices.
The data EEPROM is organized as 16-bit wide
memory. Each word is directly addressable, and is
readable and writable during normal operation over the
entire V
Unlike the Flash program memory, normal program
execution is not stopped during a data EEPROM
program or erase operation.
The data EEPROM programming operations are
controlled using the three NVM Control registers:
• NVMCON: Nonvolatile Memory Control Register
• NVMKEY: Nonvolatile Memory Key Register
• NVMADR: Nonvolatile Memory Address Register
EXAMPLE 6-1:
© 2009 Microchip Technology Inc.
//Disable Interrupts For 5 instructions
asm volatile(“disi #5”);
//Issue Unlock Sequence
asm volatile(“mov #0x55, W0
// Perform Write/Erase operations
asm volatile (“bset NVMCON, #WR
Note:
DD
DATA EEPROM MEMORY
range.
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on Data
EEPROM, refer to the “PIC24F Family
Reference Manual”, Section 5. “Data
EEPROM” (DS39720).
“mov W0, NVMKEY
“mov #0xAA, W1
“mov W1, NVMKEY
“nop
“nop
DATA EEPROM UNLOCK SEQUENCE
\n”
\n”
\n”
\n”);
\n”);
\n”
\n”
Preliminary
PIC24F16KA102 FAMILY
6.1
The NVMCON register (Register 6-1) is also the pri-
mary control register for data EEPROM program/erase
operations. The upper byte contains the control bits
used to start the program or erase cycle, and the flag
bit to indicate if the operation was successfully
performed. The lower byte of NVMCOM configures the
type of NVM operation that will be performed.
6.2
The NVMKEY is a write-only register that is used to
prevent accidental writes or erasures of data EEPROM
locations.
To start any programming or erase sequence, the
following instructions must be executed first, in the
exact order provided:
1.
2.
After this sequence, a write will be allowed to the
NVMCON register for one instruction cycle. In most
cases, the user will simply need to set the WR bit in the
NVMCON register to start the program or erase cycle.
Interrupts should be disabled during the unlock
sequence.
The MPLAB
procedure (builtin_write_NVM) to perform the
unlock sequence. Example 6-1 illustrates how the
unlock sequence can be performed with in-line
assembly.
Write 55h to NVMKEY.
Write AAh to NVMKEY.
NVMCON Register
NVMKEY Register
®
C30 C compiler provides a defined library
DS39927B-page 51

Related parts for PIC24F16KA101T-I/MQ