PIC24F16KA101T-I/SO Microchip Technology, PIC24F16KA101T-I/SO Datasheet
PIC24F16KA101T-I/SO
Specifications of PIC24F16KA101T-I/SO
Related parts for PIC24F16KA101T-I/SO
PIC24F16KA101T-I/SO Summary of contents
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... PIC24FXXKAXXX devices without having to deal with the low-level programming protocols of the device. Section 4.0 “Device Programming – Enhanced ICSP” describes the ICSP method using the programming executive. © 2008 Microchip Technology Inc. PIC24FXXKAXXX FIGURE 2-1: Programmer 2.1 Power Requirements All devices in the PIC24FXXKAXXX family are 3 ...
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... Refer to the appropriate device data sheet for pin descriptions MCLR PGC2 PGD2 PGD3 6 9 PGC3 MCLR PGC2 3 18 PGD2 PGD1 4 17 PGC1 PGD3 PGC3 MCLR PGD1 5 24 PGC1 6 23 PGC2 7 22 PGD2 PGC3 PGD3 PGD1 1 21 PGC1 PGC2 19 PIC24FXXKA102 4 18 PGD2 Advance Information © 2008 Microchip Technology Inc. ...
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... See Section 6.0 “Device ID” for more information. The Device ID registers read out normally even after code protection is applied. Figure 2-3 depicts the memory PIC24FXXKAXXX family variants. © 2008 Microchip Technology Inc. PIC24FXXKAXXX During Programming Pin Type Pin Description P Programming Enable P ...
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... AFEh/15FEh/2BFEh Reserved 7FFE00h (2) Data EEPROM 800000h Programming Executive Code Memory (1016 x 24-bit) 8007EEh 8007F0h Diagnostic Words 8007FEh 800800h Reserved F80000h Configuration Registers F80010h FEFFFEh FF0000h Device ID FF0002h (2 x 16-bit) FF0004h Reserved FFFFFEh Advance Information (1) © 2008 Microchip Technology Inc. ...
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... Program and verify the code memory. 3. Program and verify the data EEPROM memory. 4. Program and verify the device configuration. 5. Program the code-protect Configuration bits if required. © 2008 Microchip Technology Inc. PIC24FXXKAXXX FIGURE 3-1: to the Program Data EEPROM Memory Verify Data EEPROM Memory Program Configuration Bits Verify Configuration Bits 3 ...
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... Data changes on the falling edge and latches on the rising edge of PGCx. For all Significant bit (LSb) is transmitted first. Advance Information #0x0,W0 followed by MOV of invalid memory spaces are data transmissions, the Least © 2008 Microchip Technology Inc. ...
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... PGDx Execute PC – 1, Fetch SIX Only for Control Code Program Memory Entry FIGURE 3-3: REGOUT SERIAL EXECUTION PGCx P4 PGDx Execute Previous Instruction, CPU Held in Idle Fetch REGOUT Control Code PGDx = Input © 2008 Microchip Technology Inc. PIC24FXXKAXXX P1A P1B LSB 24-Bit Instruction Fetch ...
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... While in ICSP mode, all unused I/Os are placed in a must be high-impedance state ... b29 b28 b27 P1A P1B IHH ... 0 b29 b28 b27 P1A P1B Advance Information PP , must be held at that level for IHH P19 © 2008 Microchip Technology Inc. ...
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... Erase Configuration registers except FBS and FGS. Note 1: The destination address decides the region (code memory, data EEPROM memory or Configuration register) of the erased rows/words. © 2008 Microchip Technology Inc. PIC24FXXKAXXX TABLE 3-3: NVMCON VALUES FOR WRITE OPERATIONS NVMCON Value (1) 4004h Write one Configuration register ...
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... NVMCON register in Steps 7 and 8. In Step 9, the internal PC is reset to 200h. This is a precautionary measure to prevent the PC from incrementing to unimplemented memory when large devices are being programmed. Finally, in Step 10, repeat Steps 3 through 9 until all of the code memory is programmed. Advance Information © 2008 Microchip Technology Inc. ...
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... MOV 0000 2xxxx1 MOV 0000 2xxxx2 MOV 0000 2xxxx3 MOV 0000 2xxxx4 MOV 0000 2xxxx5 MOV © 2008 Microchip Technology Inc. PIC24FXXKAXXX 0 MSB0 MSB2 Description 0x200 #0x4004, W10 W10, NVMCON #<DestinationAddress23:16>, W0 W0, TBLPAG #<DestinationAddress15:0>, W7 #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3>, W5 ...
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... Step 9: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 10: Repeat Steps 3 through 9 until the entire code memory is programmed. DS39919A-page 12 Description W6 [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] NVMCON, #WR 0x200 NVMCON, W2 W2, VISI 0x200 Advance Information © 2008 Microchip Technology Inc. ...
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... FIGURE 3-8: PROGRAM CODE MEMORY FLOW LoopCount = LoopCount + 1 © 2008 Microchip Technology Inc. PIC24FXXKAXXX Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> All No bytes written? Yes Start Write Sequence and Poll for WR bit to be Cleared All No locations done? ...
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... EEPROM). Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> Start Write Sequence and Poll for WR bit to be Cleared All No locations done? Yes End Advance Information © 2008 Microchip Technology Inc. ...
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... NOP Step 7: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 8: Repeat Steps 4 through 7 until the entire data EEPROM memory is programmed. © 2008 Microchip Technology Inc. PIC24FXXKAXXX Description 0x200 #0x4004, W10 W10, NVMCON #0x7F, W0 W0, TBLPAG #<DestinationAddress15:0>, W7 #<Data_Word_Value>, W0 W0, [W7++] ...
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... FICD, are reserved locations on PIC24F04KA2XX devices, and should be programmed with the default value given above. 4: The RTCSOSC bit (FDS<5>) is not implemented on PIC24F04KA2XX devices, and should be programmed as ‘1’. Advance Information Value 0Fh 03h 87h FFh DFh FBh C3h FFh © 2008 Microchip Technology Inc. ...
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... Step 9: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 10: Repeat Steps 5 through 9 to write other fuses, Load W6 with their respective values and W7 with their respective addresses. © 2008 Microchip Technology Inc. PIC24FXXKAXXX Command (Binary) 0x200 #0x0000, W7 #0x4004, W10 W10, NVMCON #0xF8, W6 W0, TBLPAG #< ...
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... VISI register, using the REGOUT command. Step 4 is repeated until the required amount of code memory is read. Description 0x200 #<SourceAddress23:16>, W0 W0, TBLPAG #<SourceAddress15:0>, W6 #VISI, W7 [W6], [W7] [W6++], [W7] [++W6], [W7--] [W6++], [W7] 0x200 Advance Information © 2008 Microchip Technology Inc. ...
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... Step 6: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP © 2008 Microchip Technology Inc. PIC24FXXKAXXX Table 3-10 provides the ICSP programming details for reading data memory. Note: The TBLPAG register is hard-coded to 0x7F (the upper byte address of all locations of data memory). ...
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... Configuration registers. Note: The hard-coded to 0xF8 (the upper byte address of the Configuration register) and the Read Pointer, W6, is initialized to 0x00h. Description 0x200 #0xF8, W0 W0, TBLPAG #0x0000,W6 #VISI, W7 [W6++], [W7] 0x200 Advance Information TBLPAG register should be © 2008 Microchip Technology Inc. ...
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... Yes All No code memory verified? Yes End © 2008 Microchip Technology Inc. PIC24FXXKAXXX 3.13 Reading the Application ID Word The Application ID Word is stored in address 8005BEh in the executive code memory. To read this memory location, use the SIX control code to move this program memory location to the VISI register. Then, the REGOUT control code must be used to clock the contents of the VISI register out of the device ...
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... NOP 0000 000000 NOP Step 3: Output the VISI register using the REGOUT command. Clock out contents of the VISI register. 0001 <VISI> 0000 000000 NOP DS39919A-page 22 Description 0x200 #0x80, W0 W0, TBLPAG #0x5BE, W0 #VISI, W1 [W0], [W1] Advance Information © 2008 Microchip Technology Inc. ...
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... QVER The programming executive uses the device’s data RAM for variable storage and program execution. After the programming executive is run, no assumptions should be made about the contents of the data RAM. © 2008 Microchip Technology Inc. PIC24FXXKAXXX 4.1 Overview of the Programming Process Figure 4-1 illustrates the high-level overview of the programming process ...
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... Advance Information the case After V is removed 0100 0011 0100 1000 0101 format). The device will enter must be IH for entering Enhanced ICSP pin is the same should be IHH . The voltage must be applied to IH © 2008 Microchip Technology Inc. , ...
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... PROGP programs one row of code memory, starting from the memory address specified in the command. The number of PROGP commands required to program a device depends on the number of write blocks that must be programmed in the device. © 2008 Microchip Technology Inc. PIC24FXXKAXXX V IH Program/Verify Entry Code = 4D434850h ...
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... The READD No command reads back the programmed data EEPROM. Alternatively, the programmer can perform the verification once the entire device is programmed using a checksum Section 6.1.1 “Checksum Computation”. Failure Report Error Advance Information computation, as described in © 2008 Microchip Technology Inc. ...
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... Device ID Bits These are read-only bits, which are located from FF0000 to FF0003, and are unique to every device. Table 4-2 provides the Configuration registers. © 2008 Microchip Technology Inc. PIC24FXXKAXXX 4.7.1 PROGRAMMING METHODOLOGY Configuration bits may be programmed, a single byte at a time, using the PROGP command ...
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... Background debugger functions enabled Deep Sleep Watchdog Timer Enable bit 1 = DSWDT enabled 0 = DSWDT disabled DSWDT Reference Clock Select bit 1 = DSWDT uses LPRC as reference clock 0 = DSWDT uses SOSC as reference clock -Based Test mode entry. This prevents a user PP Advance Information © 2008 Microchip Technology Inc. ...
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... Applies only to the 28-pin device. 2: The MCLRE fuse can only be changed when using the V from accidentally locking out the device from low-voltage test entry. © 2008 Microchip Technology Inc. PIC24FXXKAXXX Description Deep Sleep Watchdog Timer Postscale Select bits The DSWDT prescaler is 32; this creates an approximate base time unit ...
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... Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 Windowed Watchdog Timer Disable bit 1 = Standard WDT selected; windowed WDT disabled 0 = Windowed WDT enabled -Based Test mode entry. This prevents a user PP Advance Information © 2008 Microchip Technology Inc. ...
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... To exit the Program/Verify mode, remove V MCLR illustrated in Figure 4-8. For exiting interval P16 should elapse between the last clock and program signals on PGCx and PGDx before removing © 2008 Microchip Technology Inc. PIC24FXXKAXXX Start ConfigAddress = F80000h Send PROGP Command Is No PROGP response ...
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... MHz clock be provided by the programmer. FIGURE 5- PGCx P1A P1B PGDx MSb Advance Information PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA RECEIVED FROM DEVICE ... LSb PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA TRANSMITTED TO DEVICE ... LSb © 2008 Microchip Technology Inc. ...
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... Length Command Data First Word (if required) • • Command Data Last Word (if required) © 2008 Microchip Technology Inc. PIC24FXXKAXXX As a safety measure, the programmer should use the command time-outs identified and listed in Table 5-1. If the command time-out expires, the programmer should ...
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... This command is reserved. it returns a NACK. 1 msec/word Read up to (256) 16-bit words starting from the specified address. 5 msec Program one word of data EEPROM memory at the specified address and then verify. Advance Information executive will “NACK” all Description (1) (1) (1) © 2008 Microchip Technology Inc. ...
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... Addr_MSB and Addr_LS. Note: This command can only be used to read 8-bit or 16-bit data. © 2008 Microchip Technology Inc. PIC24FXXKAXXX When this command is used to read the Device ID registers, the upper byte in every data word returned by the programming executive is 00h and the lower byte contains the Device ID register value. “ ...
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... Addr_MSB and Addr_LS. Once one word of data EEPROM has been programmed, the programming executive verifies the programmed data against the data in the command. Advance Information Length Addr_MSB Addr_LS Data Description Length Addr_MSB Addr_LS D_1 Description © 2008 Microchip Technology Inc. ...
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... Only one Configuration Word at a time can be programed. The unimplemented bits of the Configuration Word should be stuffed with ‘1’s. Expected Response (2 words): 1500h 0002h Note: Refer to Table 2-3 for code memory size information. © 2008 Microchip Technology Inc. PIC24FXXKAXXX 5.2.12 QBLANK COMMAND Opcode Reserved Field ...
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... As the program- ming executive can process only one command at a time, this field is technically not required. However, it can be used to verify if the programming executive correctly received the command that the programmer transmitted. Advance Information QE_Code Length ... Description © 2008 Microchip Technology Inc. ...
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... With the exception of the response for the READP command, the length of each response is only two words. © 2008 Microchip Technology Inc. PIC24FXXKAXXX The response to the READP command uses the packed instruction word format described in Section 5.2.2 “Packed Data Format”. When reading an odd number of program memory words (N odd), the response to the READP command 1)/ words ...
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... EB0280 CLR 0000 000000 NOP DS39919A-page 40 Description 0x200 #0x80, W0 W0, TBLPAG #0x07F0, W1 #0xC, W2 [W1++],[W2++] #0x405A, W0 W0, NVMCON #0x80, W0 W0, TBLPAG #0x00, W1 W1, [W1] NVMCON, #15 0x200 NVMCON, W2 W2, VISI #0x4004, W1 W1, NVMCON #0x80, W0 W0, TBLPAG W5 Advance Information © 2008 Microchip Technology Inc. ...
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... GOTO 0000 000000 NOP Step 16: Repeat Steps 8 through 15 until all the last, but one (31) row of executive memory, has been programmed. Step 17: Repeat Steps 10 and 11, 12 times, to load the first 24 write latches. © 2008 Microchip Technology Inc. PIC24FXXKAXXX Description #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 ...
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... W6, [W5++] W7, [W5++] W8, [W5++] W9, [W5++] W10, [W5++] W11, [W5++] W12, [W5++] W13, [W5++] Table provides the procedure for reading the executive memory. Note: In Step 2 of Table 5-6, the TBLPAG register is set to 80h, such that the executive memory may be read. Advance Information © 2008 Microchip Technology Inc. ...
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... NOP Step 5: Reset the device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 6: Repeat Steps 4 and 5 until the entire executive memory is read. © 2008 Microchip Technology Inc. PIC24FXXKAXXX Description 0x200 #0x80, W0 W0, TBLPAG W6 #VISI, W7 [W6], [W7] [W6++], [W7] [++W6], [W7--] [W6++], [W7] ...
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... Checksum CFGB + SUM (0:002BFE) 0xC334 0 0x0000 CFGB + SUM (0:0015FE) 0xE434 0 0x0000 CFGB + SUM (0:000AFE) 0x74B4 0 0x0000 Advance Information DEV<7:0> REV<3:0> Chip Checksum with 0xAAAAAA at 0x00 Location and Value at Last Location 0xC136 0x0000 0xE236 0x0000 0x72B6 0x0000 © 2008 Microchip Technology Inc. ...
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... Delay Between First MCLR ↓ and First P18 T 1 KEY PGCx ↑ for Key Sequence on PGDx Delay Between Last PGCx ↓ for Key P19 T 2 KEY Sequence on PGDx and Second MCLR ↑ © 2008 Microchip Technology Inc. PIC24FXXKAXXX Min Max V 3.60 DDCORE — 50 — ...
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... Delay Between PGDx ↓ by Programming P20 T 11 DLY Executive and First PGCx↑ of Reception of Response P21 T 12 Delay Between Programming Executive DLY Command Response Words DS39919A-page 46 Min Max 23 — 8 — Advance Information Units Conditions μs — ns — © 2008 Microchip Technology Inc. ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08- Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 01/02/08 © 2008 Microchip Technology Inc. ...