PIC24F16KA101T-I/SS Microchip Technology, PIC24F16KA101T-I/SS Datasheet - Page 96

16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 16 I/O,16-bit PIC24F Family, NanoWatt

PIC24F16KA101T-I/SS

Manufacturer Part Number
PIC24F16KA101T-I/SS
Description
16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 16 I/O,16-bit PIC24F Family, NanoWatt
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr

Specifications of PIC24F16KA101T-I/SS

Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24F16KA101T-I/SS
Manufacturer:
MICROCHIR
Quantity:
20 000
PIC24F16KA102 FAMILY
REGISTER 9-1:
DS39927B-page 94
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
Reset values for these bits are determined by the FNOSC Configuration bits.
Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.
CLKLOCK: Clock Selection Lock Enabled bit
If FSCM is enabled (FCKSM1 = 1):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
If FSCM is disabled (FCKSM1 = 0):
Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
Unimplemented: Read as ‘0’
LOCK: PLL Lock Status bit
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
Unimplemented: Read as ‘0’
CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
Unimplemented: Read as ‘0’
SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit
1 = Enable secondary oscillator
0 = Disable secondary oscillator
OSWEN: Oscillator Switch Enable bit
1 = Initiate an oscillator switch to clock source specified by NOSC<2:0> bits
0 = Oscillator switch is complete
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
(2)
Preliminary
© 2009 Microchip Technology Inc.

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