PIC24FJ256DA210T-I/BG Microchip Technology, PIC24FJ256DA210T-I/BG Datasheet - Page 140

• Manufacturer Part Number: PIC24FJ256DA210T-I/BG
• Description: 16-bit, 256KB Flash, 96K RAM, USB, Graphics 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA210T-I/BG

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24FJ256DA210 FAMILY
7.4
7.4.1
To configure an interrupt source:
1.
2.
3.
4.
7.4.2
The method that is used to declare an Interrupt Service
Routine (ISR) and initialize the IVT with the correct vec-
tor address will depend on the programming language
(i.e., ‘C’ or assembler) and the language development
toolsuite that is used to develop the application. In
general, the user must clear the interrupt flag in the
appropriate IFSx register for the source of the interrupt
that the ISR handles. Otherwise, the ISR will be
re-entered immediately after exiting the routine. If the
ISR is coded in assembly language, it must be termi-
nated using a RETFIE instruction to unstack the saved
PC value, SRL value and old CPU priority level.
DS39969B-page 140
Note:
Set the NSTDIS (INTCON1<15>) control bit if
nested interrupts are not desired.
Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources may be programmed
to the same non-zero value.
Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
Enable the interrupt source by setting the
interrupt enable control bit associated with the
source in the appropriate IECx register.
Interrupt Setup Procedures
INITIALIZATION
At a device Reset, the IPCx registers are
initialized, such that all user interrupt
sources are assigned to priority level 4.
INTERRUPT SERVICE ROUTINE
(ISR)
7.4.3
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
7.4.4
All user interrupts can be disabled using the following
procedure:
1.
2.
To enable user interrupts, the POP instruction may be
used to restore the previous SR value.
Note that only user interrupts with a priority level of 7 or
less can be disabled. Trap sources (Level 8-15) cannot
be disabled.
The DISI instruction provides a convenient way to
disable interrupts of priority levels, 1-6, for a fixed
period of time. Level 7 interrupt sources are not
disabled by the DISI instruction.
Push the current SR value onto the software
stack using the PUSH instruction.
Force the CPU to priority level 7 by inclusive
ORing the value 0Eh with SRL.
TRAP SERVICE ROUTINE (TSR)
INTERRUPT DISABLE
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