PIC24FJ256DA210T-I/BG Microchip Technology, PIC24FJ256DA210T-I/BG Datasheet - Page 266

• Manufacturer Part Number: PIC24FJ256DA210T-I/BG
• Description: 16-bit, 256KB Flash, 96K RAM, USB, Graphics 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA210T-I/BG

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24FJ256DA210 FAMILY
REGISTER 18-16: U1IR: USB INTERRUPT STATUS REGISTER (DEVICE MODE ONLY)
DS39969B-page 266
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/K-0, HS
Note:
STALLIF
U-0
—
Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause
all set bits at the moment of the write to become cleared.
Unimplemented: Read as ‘0’
STALLIF: STALL Handshake Interrupt bit
1 = A STALL handshake was sent by the peripheral during the handshake phase of the transaction in
0 = A STALL handshake has not been sent
Unimplemented: Read as ‘0’
RESUMEIF: Resume Interrupt bit
1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for
0 = No K-state is observed
IDLEIF: Idle Detect Interrupt bit
1 = Idle condition is detected (constant Idle state of 3 ms or more)
0 = No Idle condition is detected
TRNIF: Token Processing Complete Interrupt bit
1 = Processing of the current token is complete; read the U1STAT register for endpoint information
0 = Processing of the current token is not complete; clear the U1STAT register or load the next token
SOFIF: Start-Of-Frame Token Interrupt bit
1 = A Start-Of-Frame token is received by the peripheral or the Start-Of-Frame threshold is reached by
0 = No Start-Of-Frame token is received or threshold reached
UERRIF: USB Error Condition Interrupt bit (read-only)
1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set
0 = No unmasked error condition has occurred
URSTIF: USB Reset Interrupt bit
1 = Valid USB Reset has occurred for at least 2.5 s; Reset state must be cleared before this bit can
0 = No USB Reset has occurred. Individual bits can only be cleared by writing a ‘1’ to the bit position
Device mode
full speed)
from STAT (clearing this bit causes the STAT FIFO to advance)
the host
this bit
be reasserted
as part of a word write operation on the entire register. Using Boolean instructions or bitwise oper-
ations to write to a single bit position will cause all set bits at the moment of the write to become
cleared.
U-0
U-0
—
—
K = Write ‘1’ to clear bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
RESUMEIF
R/K-0, HS
U-0
—
R/K-0, HS
IDLEIF
U-0
—
HS = Hardware Settable bit
‘0’ = Bit is cleared
R/K-0, HS
TRNIF
U-0
—
R/K-0, HS
SOFIF
U-0
—
 2010 Microchip Technology Inc.
x = Bit is unknown
UERRIF
U-0
R-0
—
R/K-0, HS
URSTIF
U-0
—
bit 8
bit 0