PIC24FJ256DA210T-I/BG Microchip Technology, PIC24FJ256DA210T-I/BG Datasheet - Page 358

• Manufacturer Part Number: PIC24FJ256DA210T-I/BG
• Description: 16-bit, 256KB Flash, 96K RAM, USB, Graphics 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA210T-I/BG

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24FJ256DA210 FAMILY
27.4.3
The Configuration registers are protected against
inadvertent or unwanted changes or reads in two ways.
The primary protection method is the same as that of
the RP registers – shadow registers contain a compli-
mentary value which is constantly compared with the
actual value.
TABLE 27-2:
27.5
PIC24FJ256DA210 family devices implement a JTAG
interface, which supports boundary scan device
testing.
27.6
PIC24FJ256DA210 family microcontrollers can be seri-
ally programmed while in the end application circuit.
This is simply done with two lines for clock (PGECx)
and data (PGEDx), and three other lines for power
(V
to manufacture boards with unprogrammed devices
and then program the microcontroller just before
shipping the product. This also allows the most recent
firmware or a custom firmware to be programmed.
DS39969B-page 358
DD
WPDIS
Segment Configuration Bits
), ground (V
1
0
0
0
JTAG Interface
In-Circuit Serial Programming™
CONFIGURATION REGISTER
PROTECTION
WPEND
SS
X
1
0
0
CODE SEGMENT PROTECTION CONFIGURATION OPTIONS
) and MCLR. This allows customers
WPCFG
x
x
1
0
No additional protection is enabled; all program memory protection is configured
by GCP and GWRP.
Addresses from the first address of the code page are defined by WPFP<7:0>
through the end of implemented program memory (inclusive), write/erase
protected, including Flash Configuration Words.
Address 000000h through the last address of the code page is defined by
WPFP<7:0> (inclusive), write/erase protected.
Address 000000h through the last address of code page is defined by
WPFP<7:0> (inclusive), write/erase protected and the last page, including Flash
Configuration Words are write/erase protected.
Write/Erase Protection of Code Segment
To safeguard against unpredictable events, Configura-
tion bit changes resulting from individual cell level
disruptions (such as ESD events) will cause a parity
error and trigger a device Reset.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the GCP bit is set, the source data for device
configuration is also protected as a consequence. Even
if General Segment protection is not enabled, the
device configuration can be protected by using the
appropriate code segment protection setting.
27.7
When MPLAB
in-circuit debugging functionality is enabled. This func-
tion allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pins.
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, V
ignated by the ICS Configuration bits. In addition, when
the feature is enabled, some of the resources are not
available for general use. These resources include the
first 80 bytes of data RAM and two I/O pins.
In-Circuit Debugger
DD
, V
®
SS
ICD 3 is selected as a debugger, the
and the PGECx/PGEDx pin pair des-
 2010 Microchip Technology Inc.