PIC24FJ256DA210T-I/BG Microchip Technology, PIC24FJ256DA210T-I/BG Datasheet - Page 84

• Manufacturer Part Number: PIC24FJ256DA210T-I/BG
• Description: 16-bit, 256KB Flash, 96K RAM, USB, Graphics 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA210T-I/BG

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

process is:
PIC24FJ256DA210 FAMILY
5.6.1
The user can program one row of Flash program memory
at a time. To do this, it is necessary to erase the 8-row
erase block containing the desired row. The general
1.
2.
3.
EXAMPLE 5-1:
DS39969B-page 84
; Set up NVMCON for block erase operation
; Init pointer to row to be ERASED
Read
(512 instructions) and store in data RAM.
Update the program data in RAM with the
desired new data.
Erase the block (see Example 5-1):
a)
b)
c)
d)
e)
MOV #0x4042, W0 ;
MOV W0, NVMCON
MOV #tblpage(PROG_ADDR), W0
MOV W0, TBLPAG
MOV #tbloffset(PROG_ADDR), W0
TBLWTL W0, [W0]
DISI #5
MOV.B #0x55, W0
MOV W0, NVMKEY
MOV.B #0xAA, W1 ;
MOV W1, NVMKEY
BSET NVMCON, #WR
NOP
NOP
Set the NVMOP bits (NVMCON<3:0>) to
‘0010’ to configure for block erase. Set the
ERASE
(NVMCON<14>) bits.
Write the starting address of the block to be
erased into the TBLPAG and W registers.
Write 55h to NVMKEY.
Write AAh to NVMKEY.
Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the dura-
tion of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
eight
(NVMCON<6>)
rows
ERASING A PROGRAM MEMORY BLOCK (ASSEMBLY LANGUAGE CODE)
of
program
and
memory
WREN
; Initialize NVMCON
;
; Initialize Program Memory (PM) Page Boundary SFR
; Initialize in-page EA<15:0> pointer
; Set base address of erase block
; Block all interrupts with priority <7
; for next 5 instructions
; Write the 0x55 key
; Write the 0xAA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
4.
5.
6.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 5-4.
Write the first 64 instructions from data RAM into
the program memory buffers (see Example 5-3).
Write the program block to Flash memory:
a)
b)
c)
d)
Repeat steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash
memory.
Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
Write 55h to NVMKEY.
Write AAh to NVMKEY.
Set the WR bit. The programming cycle
begins and the CPU stalls for the duration
of the write cycle. When the write to Flash
memory is done, the WR bit is cleared
automatically.
 2010 Microchip Technology Inc.